diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 17:54:56 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 10:22:07 +0000 |
| commit | 41b1edf58b46637a2b718fb7ddf5e6ec12da34c1 (patch) | |
| tree | 79c1bfe62fbb3f2860ef2b51281e2b679526dc78 /src/soc | |
| parent | 12baf2057c6ab14f3229a440d003d6acdeb512fe (diff) | |
| download | coreboot-41b1edf58b46637a2b718fb7ddf5e6ec12da34c1.tar.xz | |
soc/intel/baytrail/lpss.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/lpss.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index cdf78b7314..08c3c05d85 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -15,16 +15,15 @@ #include "chip.h" -static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, - int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END }; struct resource *bar; @@ -63,14 +62,17 @@ static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } +#define SET_IOSF_REG(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + do { \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_; \ + } while (0) + static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; -#define SET_IOSF_REG(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - *iosf_reg = LPSS_ ## name_ ## _CTL; \ - *nvs_index = LPSS_NVS_ ## name_ switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); @@ -104,6 +106,8 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) } } +#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ @@ -112,9 +116,6 @@ static void i2c_disable_resets(struct device *dev) REG_SCRIPT_END, }; -#define CASE_I2C(name_) \ - case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) - switch (dev->path.pci.devfn) { CASE_I2C(I2C1): CASE_I2C(I2C2): @@ -141,8 +142,7 @@ static void lpss_init(struct device *dev) if (iosf_reg < 0) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", - slot, func); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func); return; } dev_enable_snoop_and_pm(dev, iosf_reg); |