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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-05 07:54:28 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-03-06 11:54:17 +0000 |
| commit | 503d3247e48d803ce36e98d2064cf22220bb0dfd (patch) | |
| tree | f50d79bf985fdcf6489178ffdc9918d1f0759183 /src/soc | |
| parent | e079e5ccc2e707e5b6bd3b011e04c9138f159808 (diff) | |
| download | coreboot-503d3247e48d803ce36e98d2064cf22220bb0dfd.tar.xz | |
Remove DEFAULT_PCIEXBAR alias
The other DEFAULT_ entries are just immediate
constants.
Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/denverton_ns/acpi/northcluster.asl | 2 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/iomap.h | 1 |
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index bbfa13313a..f212557a56 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -138,7 +138,7 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { // PCIEXBAR memory range - Memory32Fixed(ReadOnly, DEFAULT_PCIEXBAR, 0x10000000) + Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) // TSEG Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) }) diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index a7548d40a3..8bcef91c2e 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -23,7 +23,6 @@ */ /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ /* Southbridge internal device IO BARs (Set to match FSP settings) */ |