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authorSridhar Siricilla <sridhar.siricilla@intel.com>2020-02-07 11:59:30 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 13:10:59 +0000
commit59c7cb7d372ee1a90972de9de933af880fd8a042 (patch)
tree3ebacface26f4772d9942f259c0484288d470e4a /src/soc
parentd16187ed2a6bf23022119c735d24c14d6fafae4b (diff)
downloadcoreboot-59c7cb7d372ee1a90972de9de933af880fd8a042.tar.xz
soc/intel/common: Check prerequisites for GLOBAL_RESET command
Check prerequisites before sending GLOBAL RESET command to CSE. TEST=Verified on hatch. Change-Id: Ia583e4033f15ec20e942202fa78e7884cf370ce4 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/cse/cse.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 041656a498..648ec6a6f1 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -608,6 +608,28 @@ uint32_t me_read_config32(int offset)
return pci_read_config32(PCH_DEV_CSE, offset);
}
+static bool cse_is_global_reset_allowed(void)
+{
+ /*
+ * Allow sending GLOBAL_RESET command only if:
+ * - CSE's current working state is Normal and current operation mode is Normal.
+ * - (or) CSE's current working state is normal and current operation mode can
+ * be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is
+ * Custom.
+ */
+ if (!cse_is_hfs1_cws_normal())
+ return false;
+
+ if (cse_is_hfs1_com_normal())
+ return true;
+
+ if (cse_is_hfs3_fw_sku_custom()) {
+ if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg())
+ return true;
+ }
+ return false;
+}
+
/*
* Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/CSE_RESET_ONLY.
*/
@@ -631,11 +653,17 @@ int cse_request_global_reset(enum rst_req_type rst_type)
size_t reply_size;
printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type);
+
if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) {
printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n");
return 0;
}
+ if (!cse_is_global_reset_allowed()) {
+ printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n");
+ return 0;
+ }
+
heci_reset();
reply_size = sizeof(reply);