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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-06-28 10:08:51 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-04 06:53:12 +0000
commit6e2d0c1b90251b4b61af582d2598cdbd38591db7 (patch)
tree05dd94e809ddb67fbb5b1c6f1d1c6a2ad5736a68 /src/soc
parent8f23b5d4343c5c8ec1f7f7d453f9d8784fc0d5a2 (diff)
downloadcoreboot-6e2d0c1b90251b4b61af582d2598cdbd38591db7.tar.xz
arch/x86: Adjust size of postcar stack
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient. The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB. Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/romstage.c2
-rw-r--r--src/soc/intel/apollolake/romstage.c2
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c4
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c5
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c3
-rw-r--r--src/soc/intel/denverton_ns/romstage.c3
-rw-r--r--src/soc/intel/icelake/romstage/romstage.c3
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c3
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c2
9 files changed, 14 insertions, 13 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 12ee2a8aca..000d100fa3 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -153,7 +153,7 @@ asmlinkage void car_stage_entry(void)
printk(BIOS_ERR, "Failed to set romstage handoff data\n");
post_code(0x44);
- if (postcar_frame_init(&pcf, 1 * KiB))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/*
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 5bf501dcfa..5d65a0029e 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -240,7 +240,7 @@ asmlinkage void car_stage_entry(void)
else
printk(BIOS_ERR, "Failed to determine variable data\n");
- if (postcar_frame_init(&pcf, 1*KiB))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
mainboard_save_dimm_info();
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 5621dd16eb..7e2bb64ba6 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -238,8 +238,6 @@ void romstage_common(struct romstage_params *params)
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
static void platform_enter_postcar(void)
@@ -247,7 +245,7 @@ static void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 9bca716447..9c86809368 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -16,6 +16,7 @@
#include <stddef.h>
#include <stdint.h>
#include <arch/cbfs.h>
+#include <arch/cpu.h>
#include <bootblock_common.h>
#include <bootmode.h>
#include <cbmem.h>
@@ -34,8 +35,6 @@
#include <soc/romstage.h>
#include <soc/spi.h>
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-
/* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */
@@ -44,7 +43,7 @@ void platform_enter_postcar(void)
struct postcar_frame pcf;
uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 9dadb2d14e..94b9899422 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <console/console.h>
@@ -146,7 +147,7 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 1 * KiB))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/*
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 4477c927e9..6d8eaab9b1 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <arch/io.h>
#include <cbmem.h>
#include <cf9_reset.h>
@@ -161,7 +162,7 @@ asmlinkage void car_stage_entry(void)
display_fsp_smbios_memory_info_hob();
#endif
- if (postcar_frame_init(&pcf, 1 * KiB))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/*
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index b0eeb2e959..514e5e8925 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
#include <console/console.h>
@@ -131,7 +132,7 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 1 * KiB))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/*
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 5ebbacbd2a..a8bd26eceb 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
#include <arch/symbols.h>
#include <console/console.h>
#include <cbmem.h>
@@ -61,7 +62,7 @@ asmlinkage void car_stage_c_entry(void)
/* Initialize the PCIe bridges */
pcie_init();
- if (postcar_frame_init(&pcf, 1*KiB))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/* Locate the top of RAM */
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 6ff59bad65..fafa343780 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -158,7 +158,7 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 1*KiB))
+ if (postcar_frame_init(&pcf, 0))
die("Unable to initialize postcar frame.\n");
/*