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| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-07-24 14:29:06 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-12-31 17:32:24 +0100 |
| commit | 7100cf2b404887e4f196286e72232153ba3f0524 (patch) | |
| tree | 0c0f6f4d436240c097a183b087f2e7fe025bc9b5 /src/soc | |
| parent | 1136447a37749135dfe172da56f9c06f3d50c664 (diff) | |
| download | coreboot-7100cf2b404887e4f196286e72232153ba3f0524.tar.xz | |
imgtec/pistachio: Add SOC_REGISTERS memory region
When used with a U-boot payload it will need this region
identity mapped also, so we're defining it in preparation
for that functionality.
Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12768
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index edf9c41493..a0b48b2e6d 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -29,6 +29,8 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00200000, 512K) RAMSTAGE(0x00280000, 128K) + /* 0x18100000 -> 0x18540000 */ + SOC_REGISTERS(0x18100000, 0x440000) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock * and then through the identity mapping in ROM stage. |