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authorYork Yang <york.yang@intel.com>2015-10-19 13:35:21 -0700
committerMartin Roth <martinroth@google.com>2015-11-16 17:43:18 +0100
commit72e33a75cb68de1048d8b12f296de1be4cb08c9b (patch)
tree663047551d6a70303639db3a56e84788cbfa032d /src/soc
parentf41ad02c83b66e72d68801413a15cf869bc97268 (diff)
downloadcoreboot-72e33a75cb68de1048d8b12f296de1be4cb08c9b.tar.xz
intel/fsp_baytrail: Load APs microcode in baytrail_init_cpus
Load microcode to APs when performing baytrail_init_cpus. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/12095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/fsp_baytrail/Makefile.inc1
-rw-r--r--src/soc/intel/fsp_baytrail/cpu.c4
-rw-r--r--src/soc/intel/fsp_baytrail/ramstage.c1
3 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index e52bceb18c..f0b69ae69d 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -22,6 +22,7 @@ subdirs-y += ../../../cpu/x86/mtrr
subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../cpu/x86/cache
+subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../lib/fsp
subdirs-y += fsp
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index b2eafd1682..2f6defc3e6 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -76,11 +76,11 @@ void baytrail_init_cpus(device_t dev)
setup_lapic();
mp_params.num_cpus = pattrs->num_cpus,
- mp_params.parallel_microcode_load = 0,
+ mp_params.parallel_microcode_load = 1,
mp_params.adjust_apic_id = adjust_apic_id;
mp_params.flight_plan = &mp_steps[0];
mp_params.num_records = ARRAY_SIZE(mp_steps);
- mp_params.microcode_pointer = 0;
+ mp_params.microcode_pointer = pattrs->microcode_patch;
if (mp_init(cpu_bus, &mp_params)) {
printk(BIOS_ERR, "MP initialization failure.\n");
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c
index 53ae2b72ea..ff2b0a65f8 100644
--- a/src/soc/intel/fsp_baytrail/ramstage.c
+++ b/src/soc/intel/fsp_baytrail/ramstage.c
@@ -89,6 +89,7 @@ static void fill_in_pattrs(void)
attrs->stepping += STEP_A0;
}
+ attrs->microcode_patch = intel_microcode_find();
attrs->address_bits = cpuid_eax(0x80000008) & 0xff;
detect_num_cpus(attrs);