summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorJoseph Lo <josephl@nvidia.com>2014-06-27 11:22:41 +0800
committerMarc Jones <marc.jones@se-eng.com>2015-01-09 16:50:23 +0100
commit749559b1fbee31395c93fa25f9db708d414d3a79 (patch)
tree7cc9c0cb12b1634674ac4b505374bd4d63084190 /src/soc
parent0b5b541373bd5853d2fd6093c32d46d8f6003dd0 (diff)
downloadcoreboot-749559b1fbee31395c93fa25f9db708d414d3a79.tar.xz
tegra124: fix and fine tune the warm boot code
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same as PLLP. But that is incorrect, BootROM had switched it to pllp_out2 with the rate 204MHz. So actually the warm boot procedure was running at the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz. And the CPU complex power on sequences were different with what we used in kernel and Coreboot. Fix up the sequence as below. * enable CPU clk * power on CPU complex * remove I/O clamps * remove CPU reset Update the time of the CPU complex power on function for record. * power_on_partition(PARTID_CRAIL): 528 uSec * power_on_partition(PARTID_CONC): 0 uSec * power_on_partition(PARTID_CE0): 4 uSec Finally, removing the redundant routine of a flow controller event with (20 | MSEC_EVENT | MODE_STOP). BUG=chrome-os-partner:29394 BRANCH=none TEST=manually test LP0 with lid switch quickly and make sure the last write to restore register successfully Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/205901 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If21d17dc888b2c289970163e4f695423173ca03d Reviewed-on: http://review.coreboot.org/8151 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c27
1 files changed, 14 insertions, 13 deletions
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 0b519d6794..9b1a4b5562 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -419,6 +419,13 @@ static void config_tsc(void)
setbits32(TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG, sysctr_cntcr_ptr);
}
+static void enable_cpu_clocks(void)
+{
+ // Enable the CPU complex clock.
+ write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
+ write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+}
+
/* Function unit configuration. */
@@ -505,15 +512,15 @@ static void power_on_main_cpu(void)
* Note that PMC_CPUPWRGOOD_TIMER is running at pclk.
*
* We need to reprogram PMC_CPUPWRGOOD_TIMER based on the current pclk
- * which is at 408Mhz (pclk = sclk = pllp_out0) after reset. Multiply
- * PMC_CPUPWRGOOD_TIMER by 408M / 32K.
+ * which is at 204Mhz (pclk = sclk = pllp_out2) after BootROM. Multiply
+ * PMC_CPUPWRGOOD_TIMER by 204M / 32K.
*
* Save the original PMC_CPUPWRGOOD_TIMER register which we need to
* restore after the CPU is powered up.
*/
uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
- write32(orig_timer * (408000000 / 32768),
+ write32(orig_timer * (204000000 / 32768),
pmc_ctlr_cpupwrgood_timer_ptr);
if (wakeup_on_lp()) {
@@ -525,10 +532,6 @@ static void power_on_main_cpu(void)
power_on_partition(PARTID_CE0);
}
- // Give I/O signals time to stablize.
- write32(20 | EVENT_MSEC | FLOW_MODE_STOP,
- flow_ctlr_halt_cop_events_ptr);
-
// Restore the original PMC_CPUPWRGOOD_TIMER.
write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
}
@@ -575,12 +578,6 @@ void lp0_resume(void)
ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
- // Enable the CPU complex clock.
- write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
- write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
-
- clear_cpu_resets();
-
config_tsc();
// Disable VPR.
@@ -588,8 +585,12 @@ void lp0_resume(void)
write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
mc_video_protect_reg_ctrl_ptr);
+ enable_cpu_clocks();
+
power_on_main_cpu();
+ clear_cpu_resets();
+
// Halt the AVP.
while (1)
write32(FLOW_MODE_STOP | EVENT_JTAG,