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| author | Aaron Durbin <adurbin@chromium.org> | 2013-12-09 13:41:32 -0600 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-09 05:41:29 +0200 |
| commit | 7538937d6e7c474dc7c17a1bc3c3591f0e6ef311 (patch) | |
| tree | 65a8e907b52205692500ee9301867a1b01cbe67d /src/soc | |
| parent | f4fe3c303ca5fe8124f48973eef2f798771be0fd (diff) | |
| download | coreboot-7538937d6e7c474dc7c17a1bc3c3591f0e6ef311.tar.xz | |
rambi: export SPI write-protect GPIO correctly
Bay Trail has 3 banks of gpios. Therefore, in order to
properly identify a gpio the specific bank number as well
as the GPIO within that bank is needed. The SPI
write-protect GPIO is GPIO 6 within the SUS bank (offset
0x2000).
BUG=chrome-os-partner:24324
BUG=chrome-os-partner:24408
BRANCH=None
TEST=Built and booted. Looked at GPIO sysfs in the
chromeos_acpi directory.
Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179195
Reviewed-on: http://review.coreboot.org/4995
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions