Fix code that would trip -Wtype-limits

This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.

Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 11 insertions, 13 deletions

diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 8438ab45db..7679724ece 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -502,7 +502,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
 #define LPC_DEFAULT_IO_RANGE_LOWER 0
 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
 
-static inline int pch_io_range_in_default(u16 base, u16 size)
+static inline int pch_io_range_in_default(int base, int size)
 {
 	/* Does it start above the range? */
 	if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c
index 9d1f92d48a..438bd14757 100644
--- a/src/soc/qualcomm/ipq40xx/qup.c
+++ b/src/soc/qualcomm/ipq40xx/qup.c
@@ -478,8 +478,7 @@ qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state)
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 	unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE));
 
-	if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE)
-		&& (curr_state & QUP_STATE_VALID_MASK)) {
+	if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) {
 		/*
 		* For PAUSE_STATE to RESET_STATE transition,
 		* two writes of  10[binary]) are required for the
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index 109eda9fc0..b68e1cb864 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -648,8 +648,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
 {
 	struct ipq_spi_slave *ds = NULL;
 	int i;
-	unsigned int bus = slave->bus;
-	unsigned int cs = slave->cs;
+	int bus = slave->bus;
+	int cs = slave->cs;
 
 	if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI)
 		|| ((bus == BLSP0_SPI) && (cs > 2))
diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c
index 872b264cfa..3ceb84d881 100644
--- a/src/soc/qualcomm/ipq806x/qup.c
+++ b/src/soc/qualcomm/ipq806x/qup.c
@@ -379,8 +379,7 @@ qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state)
 	qup_return_t ret = QUP_ERR_UNDEFINED;
 	unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE));
 
-	if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE)
-		&& (curr_state & QUP_STATE_VALID_MASK)) {
+	if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) {
 		/*
 		* For PAUSE_STATE to RESET_STATE transition,
 		* two writes of  10[binary]) are required for the
diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c
index 657734524c..2657b9c574 100644
--- a/src/soc/qualcomm/ipq806x/spi.c
+++ b/src/soc/qualcomm/ipq806x/spi.c
@@ -760,8 +760,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
 {
 	struct ipq_spi_slave *ds = NULL;
 	int i;
-	unsigned int bus = slave->bus;
-	unsigned int cs = slave->cs;
+	int bus = slave->bus;
+	int cs = slave->cs;
 
 	/*
 	 * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash
diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c
index 98016c0fc9..e929419a14 100644
--- a/src/soc/rockchip/common/spi.c
+++ b/src/soc/rockchip/common/spi.c
@@ -96,7 +96,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
 
 void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
 {
-	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+	assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
 	struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
 	unsigned int ctrlr0 = 0;
 
@@ -134,13 +134,13 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
 
 void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns)
 {
-	assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves));
+	assert(bus < ARRAY_SIZE(rockchip_spi_slaves));
 	struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs;
 	unsigned int rsd;
 
 	/* Rxd Sample Delay */
 	rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8);
-	assert(rsd >= 0 && rsd <= 3);
+	assert(rsd <= 3);
 	clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET,
 			rsd << SPI_RXDSD_OFFSET);
 }
diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c
index 753a24be19..1903f6b3b9 100644
--- a/src/soc/samsung/exynos5420/spi.c
+++ b/src/soc/samsung/exynos5420/spi.c
@@ -206,7 +206,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave)
 
 static int spi_ctrlr_setup(const struct spi_slave *slave)
 {
-	ASSERT(slave->bus >= 0 && slave->bus < 3);
+	ASSERT(slave->bus < 3);
 	struct exynos_spi_slave *eslave;
 
 	eslave = to_exynos_spi(slave);