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authorJulius Werner <jwerner@chromium.org>2018-04-24 16:39:20 -0700
committerJulius Werner <jwerner@chromium.org>2018-08-07 20:55:33 +0000
commit90f025b2762edbac0516cb42f4fc7c9c28f260fa (patch)
treebd4c92e57766bb5686d6b69538b1ebe5d220189e /src/soc
parentc49ab459bc726197208134ba5585522ce4d9cad3 (diff)
downloadcoreboot-90f025b2762edbac0516cb42f4fc7c9c28f260fa.tar.xz
sdm845: Implement bitbang UART for bootblock
This patch replaces the UART in the bootblock of SDM845 with a bitbang implementation. Since SDM845 hardware UART needs a firmware blob loaded into it before it becomes usable, it is not really suited for use in the bootblock (since by the time we can read blobs from SPI, the bootblock is essentially over anyway). This solution allows us to still have some console output during early SoC initialization. Change-Id: I0c252ec83a7993edce5c4debc687f1fdd0d7b36d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/25813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/qualcomm/sdm845/Makefile.inc1
-rw-r--r--src/soc/qualcomm/sdm845/uart_bitbang.c45
2 files changed, 46 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc
index 1fddb56345..e603177317 100644
--- a/src/soc/qualcomm/sdm845/Makefile.inc
+++ b/src/soc/qualcomm/sdm845/Makefile.inc
@@ -7,6 +7,7 @@ bootblock-y += spi.c
bootblock-y += mmu.c
bootblock-y += timer.c
bootblock-y += gpio.c
+bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
################################################################################
verstage-y += spi.c
diff --git a/src/soc/qualcomm/sdm845/uart_bitbang.c b/src/soc/qualcomm/sdm845/uart_bitbang.c
new file mode 100644
index 0000000000..f39e0ef1ae
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/uart_bitbang.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/uart.h>
+#include <gpio.h>
+#include <types.h>
+
+#define UART_TX_PIN GPIO(4)
+
+static void set_tx(int line_state)
+{
+ gpio_set(UART_TX_PIN, line_state);
+}
+
+void uart_init(int idx)
+{
+ gpio_output(UART_TX_PIN, 1);
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+ uart_bitbang_tx_byte(data, set_tx);
+}
+
+void uart_tx_flush(int idx)
+{
+ /* unnecessary, PIO Tx means transaction is over when tx_byte returns */
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+ return 0; /* not implemented */
+}