summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2017-06-13 14:47:28 +0200
committerMartin Roth <martinroth@google.com>2017-06-16 16:03:34 +0200
commit9c27eda052fdf189288dc12223c0673109576725 (patch)
tree2bb5096247eb2177799dcbd9780a6fde62bb261b /src/soc
parent432ac615d018465e9808be4286c0caf2ca192cf1 (diff)
downloadcoreboot-9c27eda052fdf189288dc12223c0673109576725.tar.xz
soc/intel/braswell: Hide some Kconfig options in menuconfig
Don't allow the user to set PCIe configspace base address. Don't allow the user to set the DCACHE size and base. Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/Kconfig6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 520253add0..36af3fef09 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -55,7 +55,7 @@ config BOOTBLOCK_CPU_INIT
default "soc/intel/braswell/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS
- hex "PCIe CFG Base Address"
+ hex
default 0xe0000000
config MAX_CPUS
@@ -88,11 +88,11 @@ config SMM_RESERVED_SIZE
#
config DCACHE_RAM_BASE
- hex "Temporary RAM Base Address"
+ hex
default 0xfef00000
config DCACHE_RAM_SIZE
- hex "Temporary RAM Size"
+ hex
default 0x4000
help
The size of the cache-as-ram region required during bootblock