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authorSubrata Banik <subrata.banik@intel.com>2019-07-16 18:42:01 +0530
committerMartin Roth <martinroth@google.com>2019-07-17 16:18:52 +0000
commitb944516f66e253a325bd3c071f8810b7bd3e0416 (patch)
tree3cd5169052453e85eec099198dbaf3d2b687ec2a /src/soc
parent715d60abce937a7891516cdbeae9eef70ef05cb2 (diff)
downloadcoreboot-b944516f66e253a325bd3c071f8810b7bd3e0416.tar.xz
amd/stoneyridge/Kconfig: Enable stage cache based on HAVE_ACPI_RESUME
This patch fixes inconsistent issue with stage cache enabling with HAVE_ACPI_RESUME config enable. Only enable stage cache if CONFIG_HAVE_ACPI_RESUME=y Change-Id: I7c3b3ec4642a615e17fb3dbdedca6af8ca95ea2b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 3a8fd05200..ea0ad5f780 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -73,7 +73,7 @@ config CPU_SPECIFIC_OPTIONS
select C_ENVIRONMENT_BOOTBLOCK
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
- select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if HAVE_ACPI_RESUME
select PARALLEL_MP
select PARALLEL_MP_AP_WORK
select HAVE_SMI_HANDLER