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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-05-29 15:20:56 -0600
committerDuncan Laurie <dlaurie@chromium.org>2020-07-07 20:31:14 +0000
commitc5316ec4d675750f35ff1b383adacc2255e92d79 (patch)
tree9def7221ee37b1c5939f7a9d35e8ba5f0c0fd942 /src/soc
parent3452cb1359229b0457e9e1f6282c67fd459d4c90 (diff)
downloadcoreboot-c5316ec4d675750f35ff1b383adacc2255e92d79.tar.xz
soc/intel/common/block: Add new block DTT
Intel Dynamic Tuning Technology is the name of a PCI device on some Intel SoCs. This minimal PCI driver is only used now for SSDT generation on TGL devices. Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/dtt/Kconfig7
-rw-r--r--src/soc/intel/common/block/dtt/Makefile.inc1
-rw-r--r--src/soc/intel/common/block/dtt/dtt.c23
-rw-r--r--src/soc/intel/tigerlake/Kconfig1
4 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/dtt/Kconfig b/src/soc/intel/common/block/dtt/Kconfig
new file mode 100644
index 0000000000..063c475d53
--- /dev/null
+++ b/src/soc/intel/common/block/dtt/Kconfig
@@ -0,0 +1,7 @@
+config SOC_INTEL_COMMON_BLOCK_DTT
+ bool
+ default n
+ help
+ Minimal PCI Driver for enabling SSDT generation of Intel
+ Dynamic Tuning Technology (DTT) policies and controls, also
+ known as Intel DPTF (Dynamic Platform and Thermal Framework)
diff --git a/src/soc/intel/common/block/dtt/Makefile.inc b/src/soc/intel/common/block/dtt/Makefile.inc
new file mode 100644
index 0000000000..08f48c9e10
--- /dev/null
+++ b/src/soc/intel/common/block/dtt/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DTT) += dtt.c
diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c
new file mode 100644
index 0000000000..14987ead0a
--- /dev/null
+++ b/src/soc/intel/common/block/dtt/dtt.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static const unsigned short pci_device_ids[] = {
+ PCI_DEVICE_ID_INTEL_TGL_DTT,
+};
+
+static struct device_operations dptf_dev_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .scan_bus = scan_generic_bus,
+ .ops_pci = &pci_dev_ops_pci,
+};
+
+static const struct pci_driver pch_dptf __pci_driver = {
+ .ops = &dptf_dev_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c30519c2fa..091abb927f 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
+ select SOC_INTEL_COMMON_BLOCK_DTT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA