soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimit

Add CFL defaults for VR TDC config and provide Iccmax for additional Xeon
CPUs tested on the Prodrive/Hermes board.

Based on the following Intel documents:
* Document Number 570805 (XEON E EDS Vol 1)
* Document Number 337344 (CFL Datasheet Vol 1)
* Document Number 571264 (CFL CNP PDG)

Change-Id: I681de076318fb647c44cc8b8c42eb297018cc540
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

1 files changed, 79 insertions, 4 deletions

diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c
index dcb522dfbe..13fa7348c4 100644
--- a/src/soc/intel/cannonlake/vr_config.c
+++ b/src/soc/intel/cannonlake/vr_config.c
@@ -207,10 +207,19 @@ VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 35, 35) },
 };
 VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
-	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
 VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
-	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
+};
+VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 193, 45, 45) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 186, 45, 45) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 104, 35, 35) },
 };
 VR_CONFIG_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
 	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_ICC(11.1, 138, 45, 45) },
@@ -297,6 +306,7 @@ static const struct vr_lookup vr_config_icc[] = {
 	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
 	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
 	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
 	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S),
 	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
 	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
@@ -340,7 +350,6 @@ VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H) {
 VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_H_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.8, 2.7, 2.7) },
 };
-/* FIXME: Loadline isn't specified for S-series, using H-series default */
 VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
@@ -356,6 +365,9 @@ VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
 VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
 };
+VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 1.6, 3.1, 3.1) },
+};
 VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.1, 3.1, 3.1) },
 };
@@ -414,6 +426,7 @@ static const struct vr_lookup vr_config_ll[] = {
 	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
 	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
 	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
 	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S),
 	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
 	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
@@ -430,6 +443,59 @@ static const struct vr_lookup vr_config_ll[] = {
 };
 
 
+
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
+	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
+	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
+	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2) {
+	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
+	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
+	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 29, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4) {
+	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
+	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
+	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4) {
+	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
+	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
+	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4) {
+	{ 71, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 70, 30, 30) },
+	{ 62, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 62, 30, 30) },
+	{  0, value_not_set,  VR_CFG_ALL_DOMAINS_TDC(10, 45, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6) {
+	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6) {
+	{ 95, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 100, 30, 30) },
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 89, 30, 30) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 91, 30, 30) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8) {
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8) {
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
+};
+VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8) {
+	{ 80, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 150, 30, 30) },
+	{ 65, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 146, 30, 30) },
+	{  0, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 74, 25, 25) },
+};
 VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_ULT) {
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(4, 48, 22, 22) },
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(4, 58, 22, 22) },
@@ -447,7 +513,6 @@ VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H_8_2) {
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 125, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10,  86, 25, 25) },
 };
-
 VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_H) {
 	{  0, performance,   VR_CFG_ALL_DOMAINS_TDC(10, 92, 25, 25) },
 	{  0, baseline,      VR_CFG_ALL_DOMAINS_TDC(10, 80, 25, 25) },
@@ -471,6 +536,16 @@ VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2) {
 };
 
 static const struct vr_lookup vr_config_tdc[] = {
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_2),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_4),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_4),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_4),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_6),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_6),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_S_8),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8),
+	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8),
 	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT),
 	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_6_2),
 	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_ULT_2_2),