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authorFurquan Shaikh <furquan@google.com>2019-04-10 16:31:55 -0700
committerNico Huber <nico.h@gmx.de>2019-04-12 15:59:27 +0000
commitcef9879c3dce4d56fb327b53055d427bcd195987 (patch)
tree20c425d037f99efb2ef4e511122a2df52ee52748 /src/soc
parent237baa14331930e73a46a44abfe35adedc212dc3 (diff)
downloadcoreboot-cef9879c3dce4d56fb327b53055d427bcd195987.tar.xz
soc/intel/cannonlake: Select FSP_M_XIP
Cannon Lake and family require that FSP-M component should be XIP. This change selects FSP_M_XIP so that the right arguments are passed into cbfstool when adding this component. BUG=b:130306520 TEST=Verified that hatch boots fine to OS. Change-Id: Ifd8a829ebdc7681c81ece4540aa38cdcea7b6fac Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 55fef5af39..c30b562db9 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -60,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE