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author | John Zhao <john.zhao@intel.com> | 2020-04-24 10:24:04 -0700 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2020-04-29 17:19:26 +0000 |
commit | d7a6d61d51ebf4025484e567a20b2b50fda5a6f9 (patch) | |
tree | ec8d234f2835f0e0213c0b4b6f6fd293880b004a /src/soc | |
parent | 4e300cc780aada423b58af4aaeae457fa34ff741 (diff) | |
download | coreboot-d7a6d61d51ebf4025484e567a20b2b50fda5a6f9.tar.xz |
device/pci_id: Add Tiger Lake TCSS device ID
Add Tiger Lake TCSS USB xHCI, xDCI and Thunderbolt DMA device ID.
BUG=None
TEST=Built and booted image sucessfully.
Change-Id: Idef3850666c9f393181e0a13974b9ad79ba258ad
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc')
0 files changed, 0 insertions, 0 deletions