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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-08-28 13:22:30 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-09-08 05:31:35 +0000
commitdc87025ce41f24c8c3337176c3e38f230e7a0aa9 (patch)
tree9d69cae7f9f6d00c61bec7bd7d5a95f2dbcccd96 /src/soc
parent6727276a659968b509b79bf559dc25a71305bc6e (diff)
downloadcoreboot-dc87025ce41f24c8c3337176c3e38f230e7a0aa9.tar.xz
soc/intel/tigerlake: Skip GPIO configuration from FSP
FSP v3333 or later, provides a new UPD to Skip configuring GPIO settings from FSP. coreboot should provide all the required GPIO configuration for the platform when this UPD is set. BUG=b:166790597, b:146390704 BRANCH=none TEST=build and boot volteer proto2 Cq-Depend:chromium-internal:3240396,chromium-internal:2870145 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: If32f35a188d510db8e4d8973cae78297d49a9240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44913 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 2ba276d70a..4b68cb68c5 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -87,6 +87,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
m_cfg->PchIshEnable = is_dev_enabled(dev);
+ /* Skip GPIO configuration from FSP */
+ m_cfg->GpioOverride = 0x1;
+
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;