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authorRizwan Qureshi <rizwan.qureshi@intel.com>2019-02-17 11:04:51 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-02-22 11:07:48 +0000
commiteb503296fcd4f6e2afbf2bebda63da23354058b0 (patch)
tree3f1376667e480d6201466655310295c427d3242a /src/soc
parent3ba6caf81eb41247f21b9afccb30e15357ec101c (diff)
downloadcoreboot-eb503296fcd4f6e2afbf2bebda63da23354058b0.tar.xz
soc/intel/cannonlake: Add ASL function for setting pad mode
Add a function in gpio ASL library to set pad mode. BUG=b:123350329 Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/31444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/acpi/gpio_op.asl22
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_defs.h2
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h2
3 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl
index 0618601b9e..0c89e998c1 100644
--- a/src/soc/intel/cannonlake/acpi/gpio_op.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl
@@ -72,3 +72,25 @@ Method (CTXS, 1, Serialized)
}
And (Not (GPIOTXSTATE_MASK), VAL0, VAL0)
}
+
+/*
+ * Set Pad mode
+ * Arg0 - GPIO Number
+ * Arg1 - Pad mode
+ * 0 = GPIO control pad
+ * 1 = Native Function 1
+ * 2 = Native Function 2
+ * 3 = Native Function 3
+ */
+Method (GPMO, 2, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ Store (VAL0, Local0)
+ And (Not (GPIOPADMODE_MASK), Local0, Local0)
+ And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1)
+ Or (Local0, Arg1, VAL0)
+}
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index c282000d7e..e8b4f614ea 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -253,4 +253,6 @@
#define GPIORXSTATE_MASK 0x1
#define GPIORXSTATE_SHIFT 1
#define GPIOTXSTATE_MASK 0x1
+#define GPIOPADMODE_MASK 0xC00
+#define GPIOPADMODE_SHIFT 10
#endif
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
index d8d002cad0..c74c2d7c96 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
@@ -327,4 +327,6 @@
#define GPIORXSTATE_MASK 0x1
#define GPIORXSTATE_SHIFT 1
#define GPIOTXSTATE_MASK 0x1
+#define GPIOPADMODE_MASK 0xC00
+#define GPIOPADMODE_SHIFT 10
#endif