diff options
| author | Teo Boon Tiong <boon.tiong.teo@intel.com> | 2017-02-14 22:16:58 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-20 04:44:47 +0100 |
| commit | f296ce91b90ba845b1ff5ca35e98e52e884694cf (patch) | |
| tree | 7c96ba10d27827bfc24a84c610f85c0591e7c1e8 /src/soc | |
| parent | c97e042a9bda9994409869369e1cbda551dc65cf (diff) | |
| download | coreboot-f296ce91b90ba845b1ff5ca35e98e52e884694cf.tar.xz | |
soc/intel/skylake: Expand USB OC pins definition to support PCH-H
Currently the USB OC pins definition only being defined up to OC3.
For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum.
Changes is being verified and booted to Yocto with Saddle Brook.
Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/18364
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/usb.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index 77a94a8765..d4f7cc5683 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -51,6 +51,8 @@ enum { OC1, OC2, OC3, + OC4, + OC5, OC_SKIP = 8, /* Skip OC programming */ }; |