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authorCole Nelson <colex.nelson@intel.com>2017-05-16 11:38:59 -0700
committerAaron Durbin <adurbin@chromium.org>2018-04-09 17:49:18 +0000
commitf357c2562ac2b27f2520e8591a27001f39dc7e92 (patch)
tree2f114b96d02f600b65d96d2e6b079f8368ef16bd /src/soc
parentb10e96f1969bf7ab1a4c83abc484aa4873af950e (diff)
downloadcoreboot-f357c2562ac2b27f2520e8591a27001f39dc7e92.tar.xz
soc/intel/apollolake: enable MONITOR/MWAIT for GLK
MONITOR/MWAIT had an irremediable hardware bug for Apollolake. This has been fixed for GLK. Therefore, make MONITOR/MWAIT based C-states the default for GLK and disable IO-Redirection based C-states used for Apollolake. Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state residencies with and without load. Tested for S0ix entry and exit using: "echo freeze > /sys/power/state" and "suspend_stress_test -c 500". BUG=b:77639897 Change-Id: If648c25a9b26c04b278dce4af241d439790288ca Signed-off-by: Cole Nelson <colex.nelson@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/19718 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/chip.c5
-rw-r--r--src/soc/intel/apollolake/cpu.c2
2 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1dd6daf16c..cac2c0061c 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -565,9 +565,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable monitor mwait since it is broken due to a hardware bug
- * without a fix
+ * without a fix. Specific to Apollolake.
*/
- silconfig->MonitorMwaitEnable = 0;
+ if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+ silconfig->MonitorMwaitEnable = 0;
silconfig->SkipMpInit = 1;
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index d093acc06a..172a2b9708 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -45,6 +45,7 @@
#include <soc/pm.h>
static const struct reg_script core_msr_script[] = {
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
/* Enable C-state and IO/MWAIT redirect */
REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL,
(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
@@ -56,6 +57,7 @@ static const struct reg_script core_msr_script[] = {
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
/* Disable support for MONITOR and MWAIT instructions */
REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),
+#endif
/*
* Enable and Lock the Advanced Encryption Standard (AES-NI)
* feature register