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authorKarthikeyan Ramasubramanian <kramasub@chromium.org>2019-03-20 13:15:00 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-03-28 06:40:03 +0000
commitf84c103825e6999138bf97ce199657c6416ae226 (patch)
treea3c36bda0f499447d606d629b13bdbe6637107c0 /src/soc
parentcc7cdb19b10fa9b51acf8bc0fa94d202ffa214f3 (diff)
downloadcoreboot-f84c103825e6999138bf97ce199657c6416ae226.tar.xz
soc/intel/apollolake: Add support to log XHCI wake events
Add support to identify and log the XHCI wake events for apollolake into event logs. BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 6 | 2019-03-21 09:22:18 | S0ix Enter 7 | 2019-03-21 09:22:22 | S0ix Exit 8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9 9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13 10 | 2019-03-21 09:23:20 | ACPI Enter | S3 11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9 12 | 2019-03-21 09:23:30 | ACPI Wake | S3 13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13 Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32000 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/Kconfig1
-rw-r--r--src/soc/intel/apollolake/elog.c22
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 19cd296ffb..d715f39eb4 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -94,6 +94,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XDCI
select SOC_INTEL_COMMON_BLOCK_XHCI
+ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_CSE
diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c
index b03d5e65c2..c138b346e1 100644
--- a/src/soc/intel/apollolake/elog.c
+++ b/src/soc/intel/apollolake/elog.c
@@ -19,11 +19,29 @@
#include <console/console.h>
#include <elog.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/xhci.h>
#include <soc/pm.h>
#include <soc/pci_devs.h>
#include <soc/smbus.h>
#include <stdint.h>
+#define XHCI_USB2_PORT_STATUS_REG 0x480
+#if CONFIG(SOC_INTEL_GLK)
+#define XHCI_USB3_PORT_STATUS_REG 0x510
+#define XHCI_USB2_PORT_NUM 9
+#else
+#define XHCI_USB3_PORT_STATUS_REG 0x500
+#define XHCI_USB2_PORT_NUM 8
+#endif
+#define XHCI_USB3_PORT_NUM 7
+
+static const struct xhci_usb_info usb_info = {
+ .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
+ .num_usb2_ports = XHCI_USB2_PORT_NUM,
+ .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
+ .num_usb3_ports = XHCI_USB3_PORT_NUM,
+};
+
static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
{
int i;
@@ -54,6 +72,10 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
if (ps->gpe0_sts[GPE0_A] & CSE_PME_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
+ /* XHCI */
+ if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS)
+ pch_xhci_update_wake_event(&usb_info);
+
/* SMBUS Wake */
if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS)
elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);