diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-05-19 20:11:13 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-28 04:59:20 +0000 |
| commit | 0018d0f0de6517c0182137eff97ad96335bd69a8 (patch) | |
| tree | 3927989bf9b7206122aa61f47693f871486647cc /src/soc | |
| parent | e3f564988b7d893bfe681f3f93bb2a89d36f9b01 (diff) | |
| download | coreboot-0018d0f0de6517c0182137eff97ad96335bd69a8.tar.xz | |
soc/intel/jasperlake: Use coreboot lock down config
Allow lockdown configuration from using CHIPSET_LOCKDOWN_COREBOOT
config.
TEST=Build and boot waddledoo board
Change-Id: I3abaa737580ef45b98cabfa23edd84162037dd70
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41534
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 45162f91f2..eafc374584 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -7,6 +7,7 @@ #include <intelblocks/lpss.h> #include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> +#include <intelpch/lockdown.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -105,8 +106,18 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; } - /* Unlock upper 8 bytes of RTC RAM */ - params->RtcMemoryLock = 0; + /* Chipset Lockdown */ + if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { + params->PchLockDownGlobalSmi = 0; + params->PchLockDownBiosInterface = 0; + params->PchUnlockGpioPads = 1; + params->RtcMemoryLock = 0; + } else { + params->PchLockDownGlobalSmi = 1; + params->PchLockDownBiosInterface = 1; + params->PchUnlockGpioPads = 0; + params->RtcMemoryLock = 1; + } /* Enable End of Post in PEI phase */ params->EndOfPostMessage = EOP_PEI; |