diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-12-13 13:58:35 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-12-14 22:51:19 +0000 |
| commit | 14485efbb33e417330df59fcc501b336e14ef55c (patch) | |
| tree | 313782948155984f16010c72c9c27cd5009286b0 /src/soc | |
| parent | 6827cb38578ad508e8abdd73cf3eb2306b6effad (diff) | |
| download | coreboot-14485efbb33e417330df59fcc501b336e14ef55c.tar.xz | |
soc/intel/skylake: Add integrated LAN config parameters
Add parameters to configure the integrated LAN via FSP. Since
this takes over a PCI CLKREQ# pin it needs to know which pin
it should use, and there are additional parameters for LTR and
a "K1 power save" feature.
This was tested on a KBL-R board with integrated LAN, verifying
that the device is functional under Linux with the e1000e driver.
Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22856
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip_fsp20.c | 6 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a7804af14f..8540e210aa 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -135,6 +135,10 @@ struct soc_intel_skylake_config { /* Lan */ u8 EnableLan; + u8 EnableLanLtr; + u8 EnableLanK1Off; + u8 LanClkReqSupported; + u8 LanClkReqNumber; /* SATA related */ u8 EnableSata; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2df013f563..96c3b608af 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -186,6 +186,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchLanEnable = config->EnableLan; + if (config->EnableLan) { + params->PchLanLtrEnable = config->EnableLanLtr; + params->PchLanK1OffEnable = config->EnableLanK1Off; + params->PchLanClkReqSupported = config->LanClkReqSupported; + params->PchLanClkReqNumber = config->LanClkReqNumber; + } params->SataSalpSupport = config->SataSalpSupport; params->SsicPortEnable = config->SsicPortEnable; params->ScsEmmcEnabled = config->ScsEmmcEnabled; |