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authorLee Leahy <leroy.p.leahy@intel.com>2015-08-20 19:04:31 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-08 11:30:28 +0000
commit15c220dc3918755b72ac7eb1e128fc65c6b64cf7 (patch)
tree73d9bc1f3459d90c1a46d2a376e2548ff72896da /src/soc
parent11f356c3904321838d69e31f6de3a7fad9d8f42d (diff)
downloadcoreboot-15c220dc3918755b72ac7eb1e128fc65c6b64cf7.tar.xz
skylake: Remove dead code
Remove dead code not called by any part of coreboot. BRANCH=none BUG=None TEST=Build and run on skylake Change-Id: I3d457a196d12d03340bceb444d1d6c95afef13df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ea135813afeef773f37023fda58f36d544beef Original-Change-Id: Id8f4591f20d41f875348c6583618bbcaaf9d9a3a Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294953 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11544 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/include/soc/romstage.h1
-rw-r--r--src/soc/intel/skylake/romstage/spi.c20
2 files changed, 0 insertions, 21 deletions
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index f030301bdb..d1c846b045 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -33,7 +33,6 @@ void intel_early_me_status(void);
void enable_smbus(void);
int smbus_read_byte(unsigned device, unsigned address);
-int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_spi_read_wpsr(u8 *sr);
void mainboard_fill_spd_data(struct pei_data *pei_data);
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index 2194d21f58..41a144b165 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -21,26 +21,6 @@
#include <soc/flash_controller.h>
#include <soc/romstage.h>
-int early_spi_read(u32 offset, u32 size, u8 *buffer)
-{
- u32 current = 0;
-
- spi_init();
- while (size > 0) {
- u8 count = (size < 64) ? size : 64;
- /* sending NULL for spiflash struct parameter since we are not
- * calling HWSEQ read() call via Probe.
- */
- if (pch_hwseq_read(NULL, offset + current, count,
- buffer + current) != 0)
- return -1;
- size -= count;
- current += count;
- }
-
- return 0;
-}
-
/*
* Minimal set of commands to read WPSR from SPI.
* Returns 0 on success, < 0 on failure.