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authorYen Lin <yelin@nvidia.com>2015-07-16 10:23:34 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-07-23 16:44:18 +0200
commit21ee13c3ca5581c41a53a7e255709aa3c22b373a (patch)
tree7bf7b4d05c5ca670dc75fa20ac6754c4dd3c9ba4 /src/soc
parentcbaf92782ed035efd7eca615c64750a5dcdf4161 (diff)
downloadcoreboot-21ee13c3ca5581c41a53a7e255709aa3c22b373a.tar.xz
t210: lp0_resume: set CAR2PMC_CPU_ACK_WIDTH to 0
Like in cold boot path, need to set CAR2PMC_CPU_ACK_WIDTH to 0 in lp0 resume path. BUG=chrome-os-partner:40741 BRANCH=None TEST=Tested on Smaug; able to suspend/resume Change-Id: Iffd7fa4d0266e2ec482ec17e5203ceff8afe748f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 052b649b1e6a4e34d621d710ee43aec7149ab8a8 Original-Change-Id: Icdf9879469485fb37b820b30c9663eda528ac013 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/286600 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/11037 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 168c95a5d9..dc61cbac67 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -146,6 +146,13 @@ enum {
CLK_ENB_CSITE = 0x1 << 9
};
+static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr =
+ (void *)(CLK_RST_BASE + 0x388);
+enum {
+ CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0,
+ CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT
+};
+
static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440);
enum {
CLK_ENB_CPUG = 0x1 << 0,
@@ -787,6 +794,9 @@ void lp0_resume(void)
/* Disable PLLX since it isn't used in the kernel as CPU clk source. */
clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
+ /* Set CAR2PMC_CPU_ACK_WIDTH to 0 */
+ clrbits32(CAR2PMC_CPU_ACK_WIDTH_MASK, clk_rst_cpu_softrst_ctrl2_ptr);
+
/* Clear PMC_SCRATCH190 */
clrbits32(1, pmc_scratch190_ptr);