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authorFurquan Shaikh <furquan@chromium.org>2017-08-04 16:04:46 -0700
committerFurquan Shaikh <furquan@google.com>2017-08-10 16:25:00 +0000
commit3b90b5f1299053e87e718501f6c9be50dd343686 (patch)
tree83de8b47726cd3b61eb14d17b23dd78630b3eff1 /src/soc
parent3406dd64c328bf0f2f1902d42b239f84c136e4f0 (diff)
downloadcoreboot-3b90b5f1299053e87e718501f6c9be50dd343686.tar.xz
soc/intel/common/lpss: Add lpss_is_controller_in_reset
Add new API function lpss_is_controller_in_reset that returns whether the LPSS controller is in reset. Also, add lpss.c to smm stage so that lpss_is_controller_in_reset can be used in smihandler. BUG=b:64030366 Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/lpss.h3
-rw-r--r--src/soc/intel/common/block/lpss/Makefile.inc1
-rw-r--r--src/soc/intel/common/block/lpss/lpss.c11
3 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h
index 03a47144c8..138340df86 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpss.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpss.h
@@ -27,4 +27,7 @@ void lpss_reset_release(uintptr_t base);
*/
void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val);
+/* Check if controller is in reset. */
+bool lpss_is_controller_in_reset(uintptr_t base);
+
#endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */
diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc
index 50d1c10850..6ed654f750 100644
--- a/src/soc/intel/common/block/lpss/Makefile.inc
+++ b/src/soc/intel/common/block/lpss/Makefile.inc
@@ -2,3 +2,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
+smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c
diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c
index 146fdab2ed..feacef370f 100644
--- a/src/soc/intel/common/block/lpss/lpss.c
+++ b/src/soc/intel/common/block/lpss/lpss.c
@@ -39,6 +39,17 @@
/* DMA Software Reset Control */
#define LPSS_DMA_RST_RELEASE (1 << 2)
+bool lpss_is_controller_in_reset(uintptr_t base)
+{
+ uint8_t *addr = (void *)base;
+ uint32_t val = read32(addr + LPSS_RESET_CTL_REG);
+
+ if (val == 0xFFFFFFFF)
+ return true;
+
+ return !(val & LPSS_CNT_RST_RELEASE);
+}
+
void lpss_reset_release(uintptr_t base)
{
uint8_t *addr = (void *)base;