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authorFurquan Shaikh <furquan@google.com>2020-05-04 23:42:46 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-12 20:06:23 +0000
commit511aa44ee68bba15f3aa87e0b6766852436a1c65 (patch)
tree16eb88a72caf101c2e7a85b53d5aba208b6cf734 /src/soc
parent98bc961ee365f9d71ee3844e522b659519a8f8a2 (diff)
downloadcoreboot-511aa44ee68bba15f3aa87e0b6766852436a1c65.tar.xz
soc/amd/common/block/lpc: Configure io/mmio windows differently for LPC and eSPI
This change updates lpc_enable_children_resources() to configure IO and MMIO resources differently depending upon whether the mainboard wants to setup decode windows for LPC or eSPI. BUG=b:154445472,b:153675913 Change-Id: Ie8803e934f39388aeb6e3cbd7157664cb357ab23 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/common/block/lpc/lpc.c18
1 files changed, 17 insertions, 1 deletions
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 1e57bc05e5..3ddedcebe8 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -14,6 +14,7 @@
#include <pc80/i8254.h>
#include <pc80/i8259.h>
#include <amdblocks/acpimmio.h>
+#include <amdblocks/espi.h>
#include <amdblocks/lpc.h>
#include <soc/acpi.h>
#include <soc/southbridge.h>
@@ -278,6 +279,18 @@ static void configure_child_lpc_windows(struct device *dev, struct device *child
pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x);
}
+static void configure_child_espi_windows(struct device *child)
+{
+ struct resource *res;
+
+ for (res = child->resource_list; res; res = res->next) {
+ if (res->flags & IORESOURCE_IO)
+ espi_open_io_window(res->base, res->size);
+ else if (res->flags & IORESOURCE_MEM)
+ espi_open_mmio_window(res->base, res->size);
+ }
+}
+
static void lpc_enable_children_resources(struct device *dev)
{
struct bus *link;
@@ -289,7 +302,10 @@ static void lpc_enable_children_resources(struct device *dev)
continue;
if (child->path.type != DEVICE_PATH_PNP)
continue;
- configure_child_lpc_windows(dev, child);
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+ configure_child_espi_windows(child);
+ else
+ configure_child_lpc_windows(dev, child);
}
}
}