diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc')
92 files changed, 1982 insertions, 1983 deletions
diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c index 445862430a..c50de464c7 100644 --- a/src/soc/amd/picasso/uart.c +++ b/src/soc/amd/picasso/uart.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include <arch/mmio.h> #include <console/uart.h> #include <commonlib/helpers.h> +#include <device/mmio.h> #include <amdblocks/gpio_banks.h> #include <amdblocks/acpimmio.h> #include <soc/southbridge.h> diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index bd67d8a888..be15b9be8e 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -123,7 +123,7 @@ void init_timer(void) write32(>i->cc_cntrate, ((1ULL << 32) * tickrate) / sclk); /* Enable the counter */ - setbits_le32(>i->cc_cntcr, GTI_CC_CNTCR_EN); + setbits32(>i->cc_cntcr, GTI_CC_CNTCR_EN); //u32 u = (CNTPS_CTL_EL1_IMASK | CNTPS_CTL_EL1_EN); //BDK_MSR(CNTPS_CTL_EL1, u); @@ -172,11 +172,11 @@ void watchdog_set(const size_t index, unsigned int timeout_ms) printk(BIOS_DEBUG, "Watchdog: Set to expire %llu SCLK cycles\n", timeout_wdog << 18); - clrsetbits_le64(&timer->cwd_wdog[index], - (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) | - (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT), - (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) | - (3 << GTI_CWD_WDOG_MODE_SHIFT)); + clrsetbits64(&timer->cwd_wdog[index], + (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) | + (GTI_CWD_WDOG_MODE_MASK << GTI_CWD_WDOG_MODE_SHIFT), + (timeout_wdog << GTI_CWD_WDOG_LEN_SHIFT) | + (3 << GTI_CWD_WDOG_MODE_SHIFT)); } /** diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 173fa90cd7..8f1f0e64ac 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -31,7 +31,7 @@ void ovl_set_roi(u32 idx, u32 width, u32 height, u32 color) void rdma_start(void) { - setbits_le32(&disp_rdma0->global_con, RDMA_ENGINE_EN); + setbits32(&disp_rdma0->global_con, RDMA_ENGINE_EN); } void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size) @@ -39,8 +39,8 @@ void rdma_config(u32 width, u32 height, u32 pixel_clk, u32 fifo_size) u32 threshold; u32 reg; - clrsetbits_le32(&disp_rdma0->size_con_0, 0x1FFF, width); - clrsetbits_le32(&disp_rdma0->size_con_1, 0xFFFFF, height); + clrsetbits32(&disp_rdma0->size_con_0, 0x1FFF, width); + clrsetbits32(&disp_rdma0->size_con_1, 0xFFFFF, height); /* * Enable FIFO underflow since DSI and DPI can't be blocked. Set the @@ -78,5 +78,5 @@ void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height) write32(&ovl0->rdma[0].ctrl, BIT(0)); write32(&ovl0->rdma[0].mem_gmc_setting, RDMA_MEM_GMC); - setbits_le32(&ovl0->src_con, BIT(0)); + setbits32(&ovl0->src_con, BIT(0)); } diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index d60abdb964..238b1eb47f 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -120,12 +120,12 @@ static void mtk_dsi_phy_timing(int data_rate, struct mtk_phy_timing *phy_timing) static void mtk_dsi_clk_hs_mode_enable(void) { - setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); + setbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); } static void mtk_dsi_clk_hs_mode_disable(void) { - clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); + clrbits32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); } static void mtk_dsi_set_mode(u32 mode_flags) @@ -394,8 +394,8 @@ static void mtk_dsi_send_init_commands(const u8 *buf) static void mtk_dsi_reset_dphy(void) { - setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); - clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET); + setbits32(&dsi0->dsi_con_ctrl, DPHY_RESET); + clrbits32(&dsi0->dsi_con_ctrl, DPHY_RESET); } int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid, diff --git a/src/soc/mediatek/common/gpio.c b/src/soc/mediatek/common/gpio.c index 3a1a202d4d..84ba0e2e99 100644 --- a/src/soc/mediatek/common/gpio.c +++ b/src/soc/mediatek/common/gpio.c @@ -63,8 +63,7 @@ void gpio_set_mode(gpio_t gpio, int mode) pos_bit_calc_for_mode(gpio, &pos, &bit); - clrsetbits_le32(&mtk_gpio->mode[pos].val, - mask << bit, mode << bit); + clrsetbits32(&mtk_gpio->mode[pos].val, mask << bit, mode << bit); } int gpio_get(gpio_t gpio) diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index fa0b23a353..fbc2d7dfe7 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -46,17 +46,17 @@ static void mtcmos_power_on(const struct power_domain_data *pd) write32(&mtk_spm->poweron_config_set, (SPM_PROJECT_CODE << 16) | (1U << 0)); - setbits_le32(pd->pwr_con, PWR_ON); - setbits_le32(pd->pwr_con, PWR_ON_2ND); + setbits32(pd->pwr_con, PWR_ON); + setbits32(pd->pwr_con, PWR_ON_2ND); while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) || !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask)) continue; - clrbits_le32(pd->pwr_con, PWR_CLK_DIS); - clrbits_le32(pd->pwr_con, PWR_ISO); - setbits_le32(pd->pwr_con, PWR_RST_B); - clrbits_le32(pd->pwr_con, pd->sram_pdn_mask); + clrbits32(pd->pwr_con, PWR_CLK_DIS); + clrbits32(pd->pwr_con, PWR_ISO); + setbits32(pd->pwr_con, PWR_RST_B); + clrbits32(pd->pwr_con, pd->sram_pdn_mask); while (read32(pd->pwr_con) & pd->sram_ack_mask) continue; diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 2a668fe349..9271d6e6dc 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -50,8 +50,8 @@ static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave) static void spi_sw_reset(struct mtk_spi_regs *regs) { - setbits_le32(®s->spi_cmd_reg, SPI_CMD_RST_EN); - clrbits_le32(®s->spi_cmd_reg, SPI_CMD_RST_EN); + setbits32(®s->spi_cmd_reg, SPI_CMD_RST_EN); + clrbits32(®s->spi_cmd_reg, SPI_CMD_RST_EN); } void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, @@ -77,17 +77,17 @@ void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly); - clrsetbits_le32(®s->spi_cmd_reg, - (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | - SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN | - SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN | - SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN), - (SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN | - SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN)); + clrsetbits32(®s->spi_cmd_reg, + (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | + SPI_CMD_TX_ENDIAN_EN | SPI_CMD_RX_ENDIAN_EN | + SPI_CMD_TX_DMA_EN | SPI_CMD_RX_DMA_EN | + SPI_CMD_PAUSE_EN | SPI_CMD_DEASSERT_EN), + (SPI_CMD_TXMSBF_EN | SPI_CMD_RXMSBF_EN | + SPI_CMD_FINISH_IE_EN | SPI_CMD_PAUSE_IE_EN)); mtk_spi_set_gpio_pinmux(bus, pad_select); - clrsetbits_le32(®s->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, + clrsetbits32(®s->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, pad_select); gpio_output(slave->cs_gpio, 1); @@ -110,7 +110,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); struct mtk_spi_regs *regs = mtk_slave->regs; - setbits_le32(®s->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); + setbits32(®s->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); mtk_slave->state = MTK_SPI_IDLE; gpio_output(mtk_slave->cs_gpio, 0); @@ -135,10 +135,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out, else size = MIN(*bytes_in, *bytes_out); - clrsetbits_le32(®s->spi_cfg1_reg, - SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, - ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | - (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, + SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK, + ((size - 1) << SPI_CFG1_PACKET_LENGTH_SHIFT) | + (0 << SPI_CFG1_PACKET_LOOP_SHIFT)); if (*bytes_out) { const uint8_t *outb = (const uint8_t *)out; @@ -166,10 +166,10 @@ static int do_transfer(const struct spi_slave *slave, void *in, const void *out, } if (mtk_slave->state == MTK_SPI_IDLE) { - setbits_le32(®s->spi_cmd_reg, SPI_CMD_ACT_EN); + setbits32(®s->spi_cmd_reg, SPI_CMD_ACT_EN); mtk_slave->state = MTK_SPI_PAUSE_IDLE; } else if (mtk_slave->state == MTK_SPI_PAUSE_IDLE) { - setbits_le32(®s->spi_cmd_reg, SPI_CMD_RESUME_EN); + setbits32(®s->spi_cmd_reg, SPI_CMD_RESUME_EN); } stopwatch_init_usecs_expire(&sw, MTK_TXRX_TIMEOUT_US); @@ -246,7 +246,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); struct mtk_spi_regs *regs = mtk_slave->regs; - clrbits_le32(®s->spi_cmd_reg, SPI_CMD_PAUSE_EN); + clrbits32(®s->spi_cmd_reg, SPI_CMD_PAUSE_EN); spi_sw_reset(regs); mtk_slave->state = MTK_SPI_IDLE; diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c index c8af2be113..6fc2ab2fe9 100644 --- a/src/soc/mediatek/common/timer.c +++ b/src/soc/mediatek/common/timer.c @@ -48,8 +48,8 @@ void init_timer(void) timer_prepare(); /* Disable timer and clear the counter */ - clrbits_le32(&mtk_gpt->gpt6_con, GPT_CON_EN); - setbits_le32(&mtk_gpt->gpt6_con, GPT_CON_CLR); + clrbits32(&mtk_gpt->gpt6_con, GPT_CON_EN); + setbits32(&mtk_gpt->gpt6_con, GPT_CON_CLR); /* Set clock source to system clock and set clock divider to 1 */ write32(&mtk_gpt->gpt6_clk, GPT_SYS_CLK | GPT_CLK_DIV1); diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index 328bf66e0f..d80cfe98b3 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -32,53 +32,53 @@ static void phy_index_power_on(int index) if (!index) { /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ - setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); + setbits32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); /* Disable power domain ISO */ - clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); + clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); } /* Switch system IP to USB mode */ - clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); - clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); + clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); + clrbits32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); if (!index) - clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); + clrbits32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); /* Disable force settings */ - clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | + clrbits32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); - clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); + clrbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); /* Improve Rx sensitivity */ - clrsetbits_le32(&phy->u2phy.usbphyacr6, + clrsetbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); - setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); + setbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); - clrsetbits_le32(&phy->u3phya_da.reg0, + clrsetbits32(&phy->u3phya_da.reg0, P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); - clrsetbits_le32(&phy->u3phya.phya_reg9, + clrsetbits32(&phy->u3phya.phya_reg9, P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); if (!index) - clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); + clrbits32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); - clrsetbits_le32(&phy->u3phya.phya_reg6, + clrsetbits32(&phy->u3phya.phya_reg6, P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); - clrsetbits_le32(&phy->u3phyd.phyd_cdr1, + clrsetbits32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc)); - clrsetbits_le32(&phy->u3phyd.phyd_cdr1, + clrsetbits32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3)); - clrsetbits_le32(&phy->u2phy.u2phydtm1, + clrsetbits32(&phy->u2phy.u2phydtm1, P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); /* Set USB 2.0 slew rate value */ - clrsetbits_le32(&phy->u2phy.usbphyacr5, + clrsetbits32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); /* Set USB 2.0 disconnect threshold */ - clrsetbits_le32(&phy->u2phy.usbphyacr6, + clrsetbits32(&phy->u2phy.usbphyacr6, PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15)); } @@ -128,18 +128,18 @@ static int u3phy_ports_enable(void) u3p_msg("%s u2p:%d, u3p:%d\n", __func__, u2_port_num, u3_port_num); /* Power on host ip */ - clrbits_le32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN); + clrbits32(&ippc_regs->ip_pw_ctr1, CTRL1_IP_HOST_PDN); /* Power on and enable all u3 ports */ for (i = 0; i < u3_port_num; i++) { - clrsetbits_le32(&ippc_regs->u3_ctrl_p[i], + clrsetbits32(&ippc_regs->u3_ctrl_p[i], CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS, CTRL_U3_PORT_HOST_SEL); } /* Power on and enable all u2 ports */ for (i = 0; i < u2_port_num; i++) { - clrsetbits_le32(&ippc_regs->u2_ctrl_p[i], + clrsetbits32(&ippc_regs->u2_ctrl_p[i], CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS, CTRL_U2_PORT_HOST_SEL); } @@ -149,8 +149,8 @@ static int u3phy_ports_enable(void) static inline void ssusb_soft_reset(void) { /* Reset whole ip */ - setbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); - clrbits_le32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); + setbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); + clrbits32(&ippc_regs->ip_pw_ctr0, CTRL0_IP_SW_RST); } __weak void mtk_usb_prepare(void) { /* do nothing */ } diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 54ce8c0077..7d42493f84 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -45,10 +45,10 @@ int mtk_wdt_init(void) * ENABLE: disable watchdog on initialization. * Setting bit EXTEN to enable watchdog output. */ - clrsetbits_le32(&mtk_wdt->wdt_mode, - MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | - MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, - MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + clrsetbits32(&mtk_wdt->wdt_mode, + MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | + MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, + MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); return wdt_sta; } diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 9f201fd0d4..555bfe905f 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -60,17 +60,17 @@ static void main_disp_path_setup(u32 width, u32 height, u32 pixel_clk) static void disp_clock_on(void) { - clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | - CG_CON0_SMI_LARB0 | - CG_CON0_MUTEX_32K | - CG_CON0_DISP_OVL0 | - CG_CON0_DISP_RDMA0 | - CG_CON0_DISP_COLOR0 | - CG_CON0_DISP_UFOE | - CG_CON0_DISP_OD); + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_SMI_COMMON | + CG_CON0_SMI_LARB0 | + CG_CON0_MUTEX_32K | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_COLOR0 | + CG_CON0_DISP_UFOE | + CG_CON0_DISP_OD); - clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | - CG_CON1_DSI0_DIGITAL); + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DSI0_ENGINE | + CG_CON1_DSI0_DIGITAL); } void mtk_ddp_init(void) diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index f9bd5073ca..58dce72e94 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -74,17 +74,17 @@ static void mem_pll_pre_init(u32 channel) write32(&ch[channel].ddrphy_regs->mempll05_divider, 0x1 << 27); /* enable chip top memory clock */ - setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4); + setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 4); /* disable C/A and DQ M_CK clock gating */ - clrbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | - 0x1 << 1); + clrbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | + 0x1 << 1); /* enable spm control clock */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 | - 0x1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 15 | + 0x1 << 0); /* enable dramc 2X mode */ - setbits_le32(&ch[channel].ao_regs->ddr2ctl, 1 << 0); + setbits32(&ch[channel].ao_regs->ddr2ctl, 1 << 0); /* select internal clock path */ write32(&ch[channel].ddrphy_regs->peri[0], 0x21 << 24 | 0x27 << 16 | @@ -94,12 +94,12 @@ static void mem_pll_pre_init(u32 channel) 0x6 << 8 | 0x1e << 0); /* trigger to make memory clock correct phase */ - setbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 | - 0x1 << 7); + setbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 24 | + 0x1 << 7); if (channel == CHANNEL_A) { /* select memory clock sync for channel A (internal source) */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3); + clrbits32(&ch[channel].ddrphy_regs->mempll_divider, 0x1 << 3); } } @@ -156,11 +156,11 @@ static void mem_pll_init_phase_sync(u32 channel) BIT(7) | BIT(5) | BIT(4) | BIT(0)); /* spm control clock enable */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0), - BIT(1)); + clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(0), + BIT(1)); - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1), - BIT(0)); + clrsetbits32(&ch[channel].ddrphy_regs->mempll_divider, BIT(1), + BIT(0)); } static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) @@ -169,25 +169,25 @@ static void pll_phase_adjust(u32 channel, struct mem_pll *mempll, int reg_offs) case MEMPLL_INIT: /* initial phase: zero out RG_MEPLL(2,3,4)_(REF_DL,FB)_DL */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT); + clrbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT); break; case MEMPLL_REF_LAG: /* REF lag FBK, delay FBK */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT, - mempll->delay << MEMPLL_FB_DL_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT, + mempll->delay << MEMPLL_FB_DL_SHIFT); break; case MEMPLL_REF_LEAD: /* REF lead FBK, delay REF */ - clrsetbits_le32(&ch[channel].ddrphy_regs->mempll[reg_offs], - 0x1f << MEMPLL_REF_DL_SHIFT | - 0x1f << MEMPLL_FB_DL_SHIFT, - mempll->delay << MEMPLL_REF_DL_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->mempll[reg_offs], + 0x1f << MEMPLL_REF_DL_SHIFT | + 0x1f << MEMPLL_FB_DL_SHIFT, + mempll->delay << MEMPLL_REF_DL_SHIFT); }; } @@ -250,9 +250,9 @@ static void mem_pll_phase_cali(u32 channel) /* 1. set jitter meter count number to 1024 for mempll 2 3 4 */ for (i = 0; i < 3; i++) - clrsetbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_COUNTER_MASK, - JMETER_COUNT << JMETER_COUNTER_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_COUNTER_MASK, + JMETER_COUNT << JMETER_COUNTER_SHIFT); while (1) { @@ -266,8 +266,8 @@ static void mem_pll_phase_cali(u32 channel) /* 2. enable mempll 2 3 4 jitter meter */ for (i = 0; i < 3; i++) - setbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_EN_BIT); + setbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_EN_BIT); /* 3. wait for jitter meter complete */ udelay(JMETER_WAIT_DONE_US); @@ -281,8 +281,8 @@ static void mem_pll_phase_cali(u32 channel) /* 5. disable mempll 2 3 4 jitter meter */ for (i = 0; i < 3; i++) - clrbits_le32(&ch[channel].ddrphy_regs->jmeter[i], - JMETER_EN_BIT); + clrbits32(&ch[channel].ddrphy_regs->jmeter[i], + JMETER_EN_BIT); /* 6. all done early break */ if (mempll[0].done && mempll[1].done && mempll[2].done) @@ -336,58 +336,58 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params) udelay(2); /* mempll2_en -> mempll4_en -> mempll3_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); udelay(100); /* mempll_bias_lpf_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7); + setbits32(&ch[channel].ddrphy_regs->mempll[3], 1 << 7); udelay(30); /* select mempll4 band register */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); + setbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); + clrbits32(&ch[channel].ddrphy_regs->mempll[4], 1 << 26); /* PLL ready */ /* disable mempll2_en -> mempll4_en -> mempll3_en */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); /* disable autok mempll2_en -> mempll4_en -> mempll3_en */ - clrbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23); - clrbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 23); + clrbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 23); udelay(1); /* mempll[2->4->3]_fb_mck_sel=1 (switch to outer loop) */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25); - setbits_le32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25); - setbits_le32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[6], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[12], 1 << 25); + setbits32(&ch[channel].ddrphy_regs->mempll[9], 1 << 25); udelay(1); /* enable mempll2_en -> mempll4_en -> mempll3_en */ - setbits_le32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); - setbits_le32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[5], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[11], 1 << 0); + setbits32(&ch[channel].ddrphy_regs->mempll[8], 1 << 0); } /* mempll new power-on */ write32(&mtk_spm->poweron_config_set, 0x1 << 0 | SPM_PROJECT_CODE << 16); /* request mempll reset/pdn mode */ - setbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); + setbits32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(2); /* unrequest mempll reset/pdn mode and wait settle */ - clrbits_le32(&mtk_spm->power_on_val0, 0x1 << 27); + clrbits32(&mtk_spm->power_on_val0, 0x1 << 27); udelay(31); /* PLL ready */ @@ -628,16 +628,16 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ao_regs->padctl7, 0x0); /* CLKTDN, DS0TDN, DS1TDN, DS2TDN, DS3TDN */ - setbits_le32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 | + setbits32(&ch[channel].ddrphy_regs->tdsel[2], 0x1 << 31 | 0x1 << 29 | 0x1 << 27 | 0x1 << 25 | 0x1 << 1); /* DISABLE_PERBANK_REFRESH */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, 0x1 << 7); + clrbits32(&ch[channel].ao_regs->rkcfg, 0x1 << 7); /* clear R_DMREFTHD to reduce MR4 wait refresh queue time */ - clrbits_le32(&ch[channel].ao_regs->conf2, 0x7 << 24); + clrbits32(&ch[channel].ao_regs->conf2, 0x7 << 24); /* duty default value */ write32(&ch[channel].ddrphy_regs->phyclkduty, 0x1 << 28 | @@ -645,7 +645,7 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) if (!dual_rank_set) { /* single rank, CKE1 always off */ - setbits_le32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21); + setbits32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 21); } /* default dqs rx perbit input delay */ @@ -662,72 +662,72 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) void div2_phase_sync(void) { - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, + clrbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, 1 << MEMCLKENB_SHIFT); udelay(1); - setbits_le32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, + setbits32(&ch[CHANNEL_B].ddrphy_regs->mempll_divider, 1 << MEMCLKENB_SHIFT); } void dramc_phy_reset(u32 channel) { /* reset phy */ - setbits_le32(&ch[channel].ddrphy_regs->phyctl1, + setbits32(&ch[channel].ddrphy_regs->phyctl1, 1 << PHYCTL1_PHYRST_SHIFT); /* read data counter reset */ - setbits_le32(&ch[channel].ao_regs->gddr3ctl1, + setbits32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); udelay(1); /* delay 1ns */ - clrbits_le32(&ch[channel].ao_regs->gddr3ctl1, + clrbits32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); - clrbits_le32(&ch[channel].ddrphy_regs->phyctl1, + clrbits32(&ch[channel].ddrphy_regs->phyctl1, 1 << PHYCTL1_PHYRST_SHIFT); } void dramc_runtime_config(u32 channel, const struct mt8173_sdram_params *sdram_params) { - setbits_le32(&ch[channel].ddrphy_regs->dqsgctl, + setbits32(&ch[channel].ddrphy_regs->dqsgctl, BIT(17)|BIT(18)); /* enable hw gating */ - setbits_le32(&ch[channel].ao_regs->dqscal0, - 1 << DQSCAL0_STBCALEN_SHIFT); + setbits32(&ch[channel].ao_regs->dqscal0, + 1 << DQSCAL0_STBCALEN_SHIFT); /* if frequency >1600, tCKE should >7 clk */ - setbits_le32(&ch[channel].ao_regs->dummy, 0x1 << 4); + setbits32(&ch[channel].ao_regs->dummy, 0x1 << 4); if (sdram_params->dram_freq * 2 < 1600 * MHz) die("set tCKE error in runtime config"); /* DDRPHY C/A and DQ M_CK clock gating enable */ - setbits_le32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | + setbits32(&ch[channel].ddrphy_regs->ddrphy_cg_ctrl, 0x1 << 2 | 0x1 << 1); - setbits_le32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) | + setbits32(&ch[channel].ao_regs->perfctl0, BIT(19) | BIT(14) | BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(4) | BIT(0)); /* ZQCS_ENABLE */ if (sdram_params->emi_set.cona & 0x1) { /* dual channel, clear ZQCSCNT */ - clrbits_le32(&ch[channel].ao_regs->spcmd, 0xff << 16); + clrbits32(&ch[channel].ao_regs->spcmd, 0xff << 16); /* set ZQCSMASK for different channels */ if (channel == CHANNEL_A) { - clrbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); + clrbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); } else { - setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); + setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 24); } /* enable ZQCSDUAL */ - setbits_le32(&ch[channel].ao_regs->perfctl0, 0x1 << 25); + setbits32(&ch[channel].ao_regs->perfctl0, 0x1 << 25); } else { /* single channel, set ZQCSCNT */ - setbits_le32(&ch[channel].ao_regs->spcmd, 0x8 << 16); + setbits32(&ch[channel].ao_regs->spcmd, 0x8 << 16); } } @@ -736,17 +736,17 @@ void transfer_to_spm_control(void) u32 msk; msk = BIT(7) | BIT(11) | BIT(15); - clrbits_le32(&mtk_apmixed->ap_pll_con3, msk); + clrbits32(&mtk_apmixed->ap_pll_con3, msk); msk = BIT(0) | BIT(4) | BIT(8); - clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); + clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], msk); msk = BIT(0) | BIT(8); - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk); + clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[3], msk); msk = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24); - clrbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk); - clrbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk); + clrbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], msk); + clrbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], msk); } void transfer_to_reg_control(void) @@ -754,17 +754,17 @@ void transfer_to_reg_control(void) u32 val; val = BIT(7) | BIT(11) | BIT(15); - setbits_le32(&mtk_apmixed->ap_pll_con3, val); + setbits32(&mtk_apmixed->ap_pll_con3, val); val = BIT(0) | BIT(4) | BIT(8); - setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); + setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[3], val); val = BIT(0) | BIT(8); write32(&ch[CHANNEL_B].ddrphy_regs->peri[3], val); val = BIT(0) | BIT(9) | BIT(10) | BIT(11) | BIT(16) | BIT(24); - setbits_le32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val); - setbits_le32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val); + setbits32(&ch[CHANNEL_A].ddrphy_regs->peri[2], val); + setbits32(&ch[CHANNEL_B].ddrphy_regs->peri[2], val); } u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, @@ -776,9 +776,9 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, die("Invalid loopcount of engine2!"); /* Disable Test Agent1, Test Agent2 write/read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN | - CONF2_TEST2R_EN | - CONF2_TEST2W_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST1_EN | + CONF2_TEST2R_EN | + CONF2_TEST2W_EN); /* 1. set pattern, base address, offset address */ write32(&ch[channel].nao_regs->test2_1, test2_1); @@ -794,49 +794,49 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, switch (testaudpat) { case XTALK: /* TESTAUDPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 1, select xtalk pattern * TESTAUDMODE = 0, read only * TESTAUDBITINV = 0, no bit inversion */ - clrsetbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTAUDBITINV_EN | - TEST2_4_TESTAUDMODE_EN, - TEST2_4_TESTXTALKPAT_EN); + clrsetbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTAUDBITINV_EN | + TEST2_4_TESTAUDMODE_EN, + TEST2_4_TESTXTALKPAT_EN); break; case AUDIO: /* TESTAUDPAT = 1 */ - setbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + setbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 0 * TESTAUDINIT = 0x11 * TESTAUDINC = 0x0d * TESTAUDBITINV = 1 * TESTAUDMODE = 1 */ - clrsetbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTXTALKPAT_EN | - TEST2_4_TESTAUDINIT_MASK | - TEST2_4_TESTAUDINC_MASK, - TEST2_4_TESTAUDMODE_EN | - TEST2_4_TESTAUDBITINV_EN | - 0x11 << TEST2_4_TESTAUDINIT_SHIFT | - 0xd << TEST2_4_TESTAUDINC_SHIFT); + clrsetbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTXTALKPAT_EN | + TEST2_4_TESTAUDINIT_MASK | + TEST2_4_TESTAUDINC_MASK, + TEST2_4_TESTAUDMODE_EN | + TEST2_4_TESTAUDBITINV_EN | + 0x11 << TEST2_4_TESTAUDINIT_SHIFT | + 0xd << TEST2_4_TESTAUDINC_SHIFT); break; case ISI: /* TESTAUDPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_3, - TEST2_3_TESTAUDPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_3, + TEST2_3_TESTAUDPAT_EN); /* TESTXTALKPAT = 0 */ - clrbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTXTALKPAT_EN); + clrbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTXTALKPAT_EN); } /* 3. set loop number */ - clrsetbits_le32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK, - log2loopcount << TEST2_3_TESTCNT_SHIFT); + clrsetbits32(&ch[channel].ao_regs->test2_3, TEST2_3_TESTCNT_MASK, + log2loopcount << TEST2_3_TESTCNT_SHIFT); /* 4. enable read/write test */ if (wr == TE_OP_READ_CHECK) { @@ -844,15 +844,15 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, /* if audio pattern, enable read only */ /* (disable write after read), */ /* AUDMODE=0x48[15]=0 */ - clrbits_le32(&ch[channel].ao_regs->test2_4, - TEST2_4_TESTAUDMODE_EN); + clrbits32(&ch[channel].ao_regs->test2_4, + TEST2_4_TESTAUDMODE_EN); } /* enable read, 0x008[30:30] */ - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); } else if (wr == TE_OP_WRITE_READ_CHECK) { /* enable write, 0x008[31:31] */ - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); /* check "read data compare ready" bit */ do { @@ -860,8 +860,8 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, } while ((value & (1 << TESTRPT_DM_CMP_CPT_SHIFT)) == 0); /* Disable Test Agent2 write and enable Test Agent2 read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); - setbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2W_EN); + setbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); } /* 5 check "read data compare ready" bit */ @@ -876,7 +876,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2, value = read32(&ch[channel].nao_regs->cmp_err); /* 6 disable read */ - clrbits_le32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); + clrbits32(&ch[channel].ao_regs->conf2, CONF2_TEST2R_EN); /* return CMP_ERR result, pass: 0, failure: otherwise */ return value; diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 0a8e69be1e..a22d7e22d1 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -42,14 +42,14 @@ void sw_impedance_cal(u32 channel, params->impedance_drvp << 12 | params->impedance_drvn << 8; /* DQS and DQ */ - clrsetbits_le32(&ch[channel].ao_regs->iodrv6, mask, value); + clrsetbits32(&ch[channel].ao_regs->iodrv6, mask, value); /* CLK and CMD */ - clrsetbits_le32(&ch[channel].ao_regs->drvctl1, mask, value); - clrsetbits_le32(&ch[channel].ddrphy_regs->drvctl1, mask, value); + clrsetbits32(&ch[channel].ao_regs->drvctl1, mask, value); + clrsetbits32(&ch[channel].ddrphy_regs->drvctl1, mask, value); /* DQ_2 and CMD_2 */ - clrsetbits_le32(&ch[channel].ao_regs->iodrv4, mask, value); + clrsetbits32(&ch[channel].ao_regs->iodrv4, mask, value); /* disable impcal calibration */ - clrbits_le32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT | + clrbits32(&ch[channel].ao_regs->impcal, 1 << IMP_CALI_ENP_SHIFT | 1 << IMP_CALI_ENN_SHIFT | 1 << IMP_CALI_EN_SHIFT | 0xf << IMP_CALI_DRVP_SHIFT | @@ -89,40 +89,40 @@ void ca_training(u32 channel, const struct mt8173_sdram_params *sdram_params) /* set CA pins output delay */ for (i = 0; i < (CATRAINING_NUM - 1); i++) { order = ca_order[channel][i]; - clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]], - 0xf << shift[i], ca_shift[order] << shift[i]); + clrsetbits32(&ch[channel].ddrphy_regs->cmddly[cmd_order[i]], + 0xf << shift[i], ca_shift[order] << shift[i]); } order = ca_order[channel][9]; - clrsetbits_le32(&ch[channel].ddrphy_regs->dqscal0, - 0xf << DQSCAL0_RA14_SHIFT, - ca_shift[order] << DQSCAL0_RA14_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->dqscal0, + 0xf << DQSCAL0_RA14_SHIFT, + ca_shift[order] << DQSCAL0_RA14_SHIFT); /* CKE and CS delay */ ca_shift_avg32 = (u32)(ca_shift_avg8 + (CATRAINING_NUM >> 1)); ca_shift_avg32 /= (u32)CATRAINING_NUM; /* CKEDLY */ - clrsetbits_le32(&ch[channel].ddrphy_regs->cmddly[4], - 0x1f << CMDDLY4_CS_SHIFT | - 0x1f << CMDDLY4_CKE_SHIFT, - ca_shift_avg32 << CMDDLY4_CS_SHIFT | - ca_shift_avg32 << CMDDLY4_CKE_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->cmddly[4], + 0x1f << CMDDLY4_CS_SHIFT | + 0x1f << CMDDLY4_CKE_SHIFT, + ca_shift_avg32 << CMDDLY4_CS_SHIFT | + ca_shift_avg32 << CMDDLY4_CKE_SHIFT); /* CKE1DLY */ - clrsetbits_le32(&ch[channel].ao_regs->dqscal1, - 0x1f << DQSCAL1_CKE1_SHIFT, - ca_shift_avg32 << DQSCAL1_CKE1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqscal1, + 0x1f << DQSCAL1_CKE1_SHIFT, + ca_shift_avg32 << DQSCAL1_CKE1_SHIFT); /* CS1DLY */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1, - 0xf << PADCTL1_CS1_SHIFT, - ca_shift_avg32 << PADCTL1_CS1_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl1, + 0xf << PADCTL1_CS1_SHIFT, + ca_shift_avg32 << PADCTL1_CS1_SHIFT); /* set max center into clk output delay */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl1, - 0xf << PADCTL1_CLK_SHIFT, - ca_max_center << PADCTL1_CLK_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl1, + 0xf << PADCTL1_CLK_SHIFT, + ca_max_center << PADCTL1_CLK_SHIFT); dramc_dbg_msg("=========================================\n"); dramc_dbg_msg(" [Channel %d] CA training\n", channel); @@ -155,8 +155,8 @@ void write_leveling(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ddrphy_regs->padctl3, value); /* DQM */ - clrsetbits_le32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT, - (value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT); + clrsetbits32(&ch[channel].ddrphy_regs->padctl2, MASK_PADCTL2_32BIT, + (value << PADCTL2_SHIFT) & MASK_PADCTL2_32BIT); /* DQ */ for (byte_i = 0; byte_i < DQS_NUMBER; byte_i++) { @@ -203,10 +203,10 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val) curr_val_p1 = curr_val + 2; /* diff is 0.5T */ /* Rank 0 P0/P1 coarse tune settings */ - clrsetbits_le32(&ch[channel].ao_regs->dqsctl1, - 0xf << DQSCTL1_DQSINCTL_SHIFT, - coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT & - 0xf << DQSCTL1_DQSINCTL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsctl1, + 0xf << DQSCTL1_DQSINCTL_SHIFT, + coarse_tune_start << DQSCTL1_DQSINCTL_SHIFT & + 0xf << DQSCTL1_DQSINCTL_SHIFT); /* DQSINCTL does not have P1. */ /* Need to use TXDLY_DQSGATE/TXDLY_DQSGATE_P1 to set */ @@ -214,33 +214,33 @@ static void set_gw_coarse_factor(u32 channel, u8 curr_val) selph2_dqsgate = (curr_val >> 2) - coarse_tune_start; selph2_dqsgate_p1 = (curr_val_p1 >> 2) - coarse_tune_start; - clrsetbits_le32(&ch[channel].ao_regs->selph2, - 0x7 << SELPH2_TXDLY_DQSGATE_SHIFT | - 0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT, - selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT | - selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph2, + 0x7 << SELPH2_TXDLY_DQSGATE_SHIFT | + 0x7 << SELPH2_TXDLY_DQSGATE_P1_SHIFT, + selph2_dqsgate << SELPH2_TXDLY_DQSGATE_SHIFT | + selph2_dqsgate_p1 << SELPH2_TXDLY_DQSGATE_P1_SHIFT); /* dly_DQSGATE and dly_DQSGATE_P1 */ - clrsetbits_le32(&ch[channel].ao_regs->selph5, - 0x3 << SELPH5_DLY_DQSGATE_SHIFT | - 0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT, - (curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT | - (curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph5, + 0x3 << SELPH5_DLY_DQSGATE_SHIFT | + 0x3 << SELPH5_DLY_DQSGATE_P1_SHIFT, + (curr_val & 0x3) << SELPH5_DLY_DQSGATE_SHIFT | + (curr_val_p1 & 0x3) << SELPH5_DLY_DQSGATE_P1_SHIFT); } static void set_gw_fine_factor(u32 channel, u8 curr_val, u8 rank) { u32 set = curr_val & (0x7f << DQSIEN_DQS0IEN_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->dqsien[rank], - 0x7f << DQSIEN_DQS0IEN_SHIFT | - 0x7f << DQSIEN_DQS1IEN_SHIFT | - 0x7f << DQSIEN_DQS2IEN_SHIFT | - 0x7f << DQSIEN_DQS3IEN_SHIFT, - set << DQSIEN_DQS0IEN_SHIFT | - set << DQSIEN_DQS1IEN_SHIFT | - set << DQSIEN_DQS2IEN_SHIFT | - set << DQSIEN_DQS3IEN_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsien[rank], + 0x7f << DQSIEN_DQS0IEN_SHIFT | + 0x7f << DQSIEN_DQS1IEN_SHIFT | + 0x7f << DQSIEN_DQS2IEN_SHIFT | + 0x7f << DQSIEN_DQS3IEN_SHIFT, + set << DQSIEN_DQS0IEN_SHIFT | + set << DQSIEN_DQS1IEN_SHIFT | + set << DQSIEN_DQS2IEN_SHIFT | + set << DQSIEN_DQS3IEN_SHIFT); } static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl) @@ -249,33 +249,33 @@ static void set_gw_coarse_factor_rank1(u32 channel, u8 curr_val, u8 dqsinctl) curr_val_p1 = curr_val + 2; /* diff is 0.5T */ - clrsetbits_le32(&ch[channel].ao_regs->dqsctl2, - 0xf << DQSCTL2_DQSINCTL_SHIFT, - dqsinctl << DQSCTL2_DQSINCTL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->dqsctl2, + 0xf << DQSCTL2_DQSINCTL_SHIFT, + dqsinctl << DQSCTL2_DQSINCTL_SHIFT); /* TXDLY_R1DQSGATE and TXDLY_R1DQSGATE_P1 */ r1dqsgate = (curr_val >> 2) - dqsinctl; r1dqsgate_p1 = (curr_val_p1 >> 2) - dqsinctl; - clrsetbits_le32(&ch[channel].ao_regs->selph6_1, - 0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | - 0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT, - r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | - r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph6_1, + 0x7 << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | + 0x7 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT, + r1dqsgate << SELPH6_1_TXDLY_R1DQSGATE_SHIFT | + r1dqsgate_p1 << SELPH6_1_TXDLY_R1DQSGATE_P1_SHIFT); /* dly_R1DQSGATE and dly_R1DQSGATE_P1 */ - clrsetbits_le32(&ch[channel].ao_regs->selph6_1, - 0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT | - 0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT, - (curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT | - (curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT); + clrsetbits32(&ch[channel].ao_regs->selph6_1, + 0x3 << SELPH6_1_DLY_R1DQSGATE_SHIFT | + 0x3 << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT, + (curr_val & 0x3) << SELPH6_1_DLY_R1DQSGATE_SHIFT | + (curr_val_p1 & 0x3) << SELPH6_1_DLY_R1DQSGATE_P1_SHIFT); } static void dqs_gw_counter_reset(u32 channel) { /* reset dqs counter (1 to 0) */ - setbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); - clrbits_le32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + setbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + clrbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); dramc_phy_reset(channel); } @@ -357,15 +357,15 @@ void rx_dqs_gating_cal(u32 channel, u8 rank, u8 gw_coarse_val, gw_fine_val; /* disable HW gating */ - clrbits_le32(&ch[channel].ao_regs->dqscal0, + clrbits32(&ch[channel].ao_regs->dqscal0, 1 << DQSCAL0_STBCALEN_SHIFT); /* enable DQS gating window counter */ - setbits_le32(&ch[channel].ao_regs->dqsctl1, + setbits32(&ch[channel].ao_regs->dqsctl1, 1 << DQSCTL1_DQSIENMODE_SHIFT); - setbits_le32(&ch[channel].ao_regs->spcmd, + setbits32(&ch[channel].ao_regs->spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT); /* dual-phase DQS clock gating control enabling */ - setbits_le32(&ch[channel].ddrphy_regs->dqsgctl, + setbits32(&ch[channel].ddrphy_regs->dqsgctl, 1 << DQSGCTL_DQSGDUALP_SHIFT); /* gating calibration value */ @@ -418,7 +418,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel, dqsinctl = (dqsinctl >> DQSCTL1_DQSINCTL_SHIFT) & (0xf << 0); /* swap cs0 and cs1 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* rank 1 gw calibration */ rx_dqs_gating_cal(channel, 1, sdram_params); @@ -429,7 +429,7 @@ void dual_rank_rx_dqs_gating_cal(u32 channel, set_gw_fine_factor(channel, opt_gw_fine_value[channel][1], 1); /* swap cs back */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* set rank 0 coarse tune and fine tune back */ set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][0]); @@ -446,15 +446,15 @@ void dramc_rankinctl_config(u32 channel, value = min(opt_gw_coarse_value[channel][0], opt_gw_coarse_value[channel][1]) >> 2; - clrsetbits_le32(&ch[channel].ao_regs->dummy, 0xf, value); + clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value); /* RANKINCTL = RANKINCTL_ROOT1 */ - clrsetbits_le32(&ch[channel].ao_regs->dqscal1, - 0xf << 16, value << 16); + clrsetbits32(&ch[channel].ao_regs->dqscal1, + 0xf << 16, value << 16); } /* disable per-bank refresh when refresh rate >= 5 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, - 1 << RKCFG_PBREF_DISBYRATE_SHIFT); + setbits32(&ch[channel].ao_regs->rkcfg, + 1 << RKCFG_PBREF_DISBYRATE_SHIFT); } u32 dram_k_perbit(u32 channel) @@ -624,11 +624,11 @@ void clk_duty_cal(u32 channel) max_duty_sel = max_duty = 1; - clrsetbits_le32(&ch[channel].ddrphy_regs->phyclkduty, - 0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT | - 1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT, - 1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT | - max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT); + clrsetbits32(&ch[channel].ddrphy_regs->phyclkduty, + 0x3 << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT | + 1 << PHYCLKDUTY_CMDCLKP0DUTYP_SHIFT, + 1 << PHYCLKDUTY_CMDCLKP0DUTYSEL_SHIFT | + max_duty << PHYCLKDUTY_CMDCLKP0DUTYN_SHIFT); max_win_size = read32(&ch[channel].ddrphy_regs->phyclkduty); @@ -639,26 +639,26 @@ void clk_duty_cal(u32 channel) static void set_dle_factor(u32 channel, u8 curr_val) { - clrsetbits_le32(&ch[channel].ao_regs->ddr2ctl, - 0x7 << DDR2CTL_DATLAT_SHIFT, - (curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT); + clrsetbits32(&ch[channel].ao_regs->ddr2ctl, + 0x7 << DDR2CTL_DATLAT_SHIFT, + (curr_val & 0x7) << DDR2CTL_DATLAT_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->padctl4, - 0x1 << PADCTL4_DATLAT3_SHIFT, - ((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT); + clrsetbits32(&ch[channel].ao_regs->padctl4, + 0x1 << PADCTL4_DATLAT3_SHIFT, + ((curr_val >> 3) & 0x1) << PADCTL4_DATLAT3_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->phyctl1, - 0x1 << PHYCTL1_DATLAT4_SHIFT, - ((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT); + clrsetbits32(&ch[channel].ao_regs->phyctl1, + 0x1 << PHYCTL1_DATLAT4_SHIFT, + ((curr_val >> 4) & 0x1) << PHYCTL1_DATLAT4_SHIFT); - clrsetbits_le32(&ch[channel].ao_regs->misc, - 0x1f << MISC_DATLAT_DSEL_SHIFT, - (curr_val - 8) << MISC_DATLAT_DSEL_SHIFT); + clrsetbits32(&ch[channel].ao_regs->misc, + 0x1f << MISC_DATLAT_DSEL_SHIFT, + (curr_val - 8) << MISC_DATLAT_DSEL_SHIFT); /* optimize bandwidth for HW run time test engine use */ - clrsetbits_le32(&ch[channel].ao_regs->misc, - 0x1f << MISC_LATNORMP_SHIFT, - (curr_val - 3) << MISC_LATNORMP_SHIFT); + clrsetbits32(&ch[channel].ao_regs->misc, + 0x1f << MISC_LATNORMP_SHIFT, + (curr_val - 3) << MISC_LATNORMP_SHIFT); } void dual_rank_rx_datlat_cal(u32 channel, @@ -670,7 +670,7 @@ void dual_rank_rx_datlat_cal(u32 channel, r0_dle_setting = rx_datlat_cal(channel, 0, sdram_params); /* swap cs0 and cs1 */ - setbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + setbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* set rank 1 coarse tune and fine tune back */ set_gw_coarse_factor(channel, opt_gw_coarse_value[channel][1]); @@ -684,7 +684,7 @@ void dual_rank_rx_datlat_cal(u32 channel, set_gw_fine_factor(channel, opt_gw_fine_value[channel][0], 0); /* swap cs back */ - clrbits_le32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); + clrbits32(&ch[channel].ao_regs->rkcfg, MASK_RKCFG_RKSWAP_EN); /* output dle setting of rank 0 and 1 */ dramc_dbg_msg("[DLE] Rank 0 DLE calibrated setting = %xh.\n" @@ -715,7 +715,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank, channel, rank); dramc_dbg_msg("=========================================\n"); - clrbits_le32(&ch[channel].ao_regs->mckdly, + clrbits32(&ch[channel].ao_regs->mckdly, 0x11 << MCKDLY_DQIENQKEND_SHIFT | 0x1 << MCKDLY_DQIENLAT_SHIFT); diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index b6ff0bc51f..dae23f5a0c 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -40,16 +40,16 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) write32(&mipi_tx0->dsi_bg_con, reg); udelay(30); - clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, - 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); + clrsetbits32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - setbits_le32(&mipi_tx0->dsi_con, - RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); + setbits32(&mipi_tx0->dsi_con, + RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, - RG_DSI_MPPLL_SDM_PWR_ON); + clrsetbits32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + RG_DSI_MPPLL_SDM_PWR_ON); - clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); if (data_rate > 500) { txdiv0 = 0; @@ -70,9 +70,9 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) txdiv1 = 2; } - clrsetbits_le32(&mipi_tx0->dsi_pll_con0, - RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | - RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); + clrsetbits32(&mipi_tx0->dsi_pll_con0, + RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | + RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); /** * PLL PCW config @@ -86,25 +86,25 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) pcw /= 13; write32(&mipi_tx0->dsi_pll_con2, pcw); - setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + setbits32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + setbits32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); - setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + setbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + clrbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + clrbits32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); } void mtk_dsi_reset(void) { - setbits_le32(&dsi0->dsi_con_ctrl, 3); - clrbits_le32(&dsi0->dsi_con_ctrl, 1); + setbits32(&dsi0->dsi_con_ctrl, 3); + clrbits32(&dsi0->dsi_con_ctrl, 1); } void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) @@ -131,7 +131,7 @@ void mtk_dsi_pin_drv_ctrl(void) struct stopwatch sw; uint32_t pwr_ack; - setbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); + setbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDSTX_PWR_ON); stopwatch_init_usecs_expire(&sw, 1000); @@ -143,5 +143,5 @@ void mtk_dsi_pin_drv_ctrl(void) pwr_ack = read32(&lvds_tx1->vopll_ctl3) & RG_AD_LVDSTX_PWR_ACK; } while (pwr_ack == 0); - clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); + clrbits32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); } diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index be84668abe..f3ea7614e4 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -166,11 +166,11 @@ size_t sdram_size(void) static void init_4GB_mode(void) { if (sdram_size() == (size_t)4 * GiB) { - setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + setbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + setbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } else { - clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + clrbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + clrbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } } diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index e991a5f75d..c701034a52 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -25,14 +25,14 @@ */ static void set_gpi_from_mipi(void) { - setbits_le32(&mt8173_mipi->mipi_rx_ana4c, + setbits32(&mt8173_mipi->mipi_rx_ana4c, 1 << 0 | /* RG_MIPI_GPI0_IES GPI47 */ 1 << 6 | /* RG_MIPI_GPI1_IES GPI48 */ 1 << 12 | /* RG_MIPI_GPI2_IES GPI49 */ 1 << 18 | /* RG_MIPI_GPI3_IES GPI50 */ 1 << 24); /* RF_MIPI_GPI4_IES GPI51 */ - setbits_le32(&mt8173_mipi->mipi_rx_ana50, + setbits32(&mt8173_mipi->mipi_rx_ana50, 1 << 0 | /* RG_MIPI_GPI5_IES GPI52 */ 1 << 6 | /* RG_MIPI_GPI6_IES GPI53 */ 1 << 12 | /* RG_MIPI_GPI7_IES GPI54 */ diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index e1c1bff6d5..494fcadbac 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -296,7 +296,7 @@ static const struct rate rates[] = { void pll_set_pcw_change(const struct pll *pll) { - setbits_le32(pll->pcw_reg, PLL_PCW_CHG); + setbits32(pll->pcw_reg, PLL_PCW_CHG); } void mt_pll_init(void) @@ -313,7 +313,7 @@ void mt_pll_init(void) * xPLL PWR ON **************/ for (i = 0; i < APMIXED_NR_PLL; i++) - setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); + setbits32(plls[i].pwr_reg, PLL_PWR_ON); /* wait for xPLL_PWR_ON ready (min delay is 1us) */ udelay(PLL_PWR_ON_DELAY); @@ -322,7 +322,7 @@ void mt_pll_init(void) * xPLL ISO Disable *******************/ for (i = 0; i < APMIXED_NR_PLL; i++) - clrbits_le32(plls[i].pwr_reg, PLL_ISO); + clrbits32(plls[i].pwr_reg, PLL_ISO); /******************** * xPLL Frequency Set @@ -334,7 +334,7 @@ void mt_pll_init(void) * xPLL Frequency Enable ************************/ for (i = 0; i < APMIXED_NR_PLL; i++) - setbits_le32(plls[i].reg, PLL_EN); + setbits32(plls[i].reg, PLL_EN); udelay(PLL_EN_DELAY); /* wait for PLL stable (min delay is 20us) */ @@ -343,7 +343,7 @@ void mt_pll_init(void) ****************/ for (i = 0; i < APMIXED_NR_PLL; i++) { if (plls[i].rstb_shift != NO_RSTB_SHIFT) - setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); } /************** @@ -351,7 +351,7 @@ void mt_pll_init(void) ***************/ /* enable infrasys DCM */ - setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1); + setbits32(&mt8173_infracfg->top_dcmctl, 0x1); write32(&mtk_topckgen->clk_mode, 0x1); write32(&mtk_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */ @@ -374,16 +374,16 @@ void mt_pll_init(void) void mt_pll_enable_ssusb_clk(void) { /* set RG_LTECLKSQ_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1); + setbits32(&mtk_apmixed->ap_pll_con0, 0x1); udelay(100); /* wait for PLL stable */ /* set RG_LTECLKSQ_LPF_EN & DA_REF2USB_TX_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x1 << 1); - setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1); + setbits32(&mtk_apmixed->ap_pll_con0, 0x1 << 1); + setbits32(&mtk_apmixed->ap_pll_con2, 0x1); udelay(100); /* wait for PLL stable */ /* set DA_REF2USB_TX_LPF_EN & DA_REF2USB_TX_OUT_EN */ - setbits_le32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); + setbits32(&mtk_apmixed->ap_pll_con2, (0x1 << 2) | (0x1 << 1)); } @@ -391,7 +391,7 @@ void mt_pll_enable_ssusb_clk(void) void mt_pll_post_init(void) { /* CPU clock divide by 1 */ - clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff); + clrbits32(&mt8173_infracfg->top_ckdiv1, 0x3ff); /* select ARMPLL */ write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1); @@ -414,20 +414,20 @@ void mt_pll_set_aud_div(u32 rate) if (apll1) { /* mclk */ - clrbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, - mclk_div << 8); + clrbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); + clrsetbits32(&mtk_topckgen->clk_auddiv_1, 0xff << 8, + mclk_div << 8); /* bclk */ - clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, - 7 << 24); + clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 24, + 7 << 24); } else { /* mclk */ - setbits_le32(&mtk_topckgen->clk_auddiv_0, 1 << 5); - clrsetbits_le32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, - mclk_div << 8); + setbits32(&mtk_topckgen->clk_auddiv_0, 1 << 5); + clrsetbits32(&mtk_topckgen->clk_auddiv_2, 0xff << 8, + mclk_div << 8); /* bclk */ - clrsetbits_le32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, - 7 << 28); + clrsetbits32(&mtk_topckgen->clk_auddiv_0, 0xf << 28, + 7 << 28); } } @@ -441,19 +441,19 @@ void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params) u32 mpll_sdm_pcw_20_0 = 0xF13B1; /* disable MPLL for adjusting memory clk frequency */ - clrbits_le32(&mtk_apmixed->mpll_con0, BIT(0)); + clrbits32(&mtk_apmixed->mpll_con0, BIT(0)); /* MPLL configuration: mode selection */ - setbits_le32(&mtk_apmixed->mpll_con0, BIT(16)); - clrbits_le32(&mtk_apmixed->mpll_con0, 0x7 << 4); - clrbits_le32(&mtk_apmixed->pll_test_con0, 1 << 31); + setbits32(&mtk_apmixed->mpll_con0, BIT(16)); + clrbits32(&mtk_apmixed->mpll_con0, 0x7 << 4); + clrbits32(&mtk_apmixed->pll_test_con0, 1 << 31); /* set RG_MPLL_SDM_PCW for feedback divide ratio */ - clrsetbits_le32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); + clrsetbits32(&mtk_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0); } void mt_mem_pll_config_post(void) { /* power up sequence starts: enable MPLL */ - setbits_le32(&mtk_apmixed->mpll_con0, BIT(0)); + setbits32(&mtk_apmixed->mpll_con0, BIT(0)); } void mt_mem_pll_mux(void) diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index af88343c14..a15447c20f 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -170,11 +170,11 @@ s32 pwrap_init(void) s32 sub_return1 = 0; u16 rdata = 0x0; - setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + setbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* add 1us delay for toggling SW reset */ udelay(1); /* clear reset bit */ - clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); + clrbits32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* Enable DCM */ write32(&mtk_pwrap->dcm_en, 3); diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index cf2ffa264b..1b0de79e34 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -47,10 +47,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | - SPI_CFG1_TICK_DLY_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | + SPI_CFG1_TICK_DLY_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } static const struct spi_ctrlr spi_flash_ctrlr = { diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c index 5460486709..23ce5570bf 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -51,19 +51,19 @@ static void mt_auxadc_update_cali(void) } static uint32_t auxadc_get_rawdata(int channel) { - setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); + setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1))); - clrbits_le32(&mtk_auxadc->con1, 1 << channel); + clrbits32(&mtk_auxadc->con1, 1 << channel); assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12)))); - setbits_le32(&mtk_auxadc->con1, 1 << channel); + setbits32(&mtk_auxadc->con1, 1 << channel); udelay(25); assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12))); uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF; - setbits_le32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10); + setbits32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10); return value; } diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 3c2b0fd662..50d6caf776 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -42,7 +42,7 @@ static void disp_config_main_path_mutex(void) static void ovl_bgclr_in_sel(u32 idx) { - setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2)); + setbits32(&disp_ovl[idx]->datapath_con, BIT(2)); } static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, @@ -74,10 +74,10 @@ static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) static void disp_clock_on(void) { - clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); - clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | - CG_CON1_DISP_DSI0_INTERFACE); + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 | + CG_CON1_DISP_DSI0_INTERFACE); } void mtk_ddp_init(void) diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 2a36b48d5d..74fa0e2f1d 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -39,7 +39,7 @@ static void cke_fix_onoff(int option, u8 chn) off = (1 - option); } - clrsetbits_le32(&ch[chn].ao.ckectrl, + clrsetbits32(&ch[chn].ao.ckectrl, (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7)); } @@ -67,13 +67,13 @@ static void dvfs_settings(u8 freq_group) dll_idle = dll_idle << 1; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 5); - setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); - clrsetbits_le32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); + setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5); + setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29); + clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle); - setbits_le32(&ch[0].phy.misc_ctrl0, 0x3 << 19); - setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); - setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7); + setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19); + setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24); + setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7); } } @@ -120,11 +120,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) ca_dll_mode[CHANNEL_A] = DLL_MASTER; ca_dll_mode[CHANNEL_B] = DLL_SLAVE; - clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xffff); - clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xffff); - setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); - clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); + clrbits32(&ch[chn].phy.shu[0].pll[4], 0xffff); + clrbits32(&ch[chn].phy.shu[0].pll[6], 0xffff); + setbits32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18); + clrsetbits32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0); + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18); SET32_BITFIELDS(&ch[chn].ao.dvfsdll, DVFSDLL_R_BYPASS_1ST_DLL_SHU1, ca_dll_mode[chn] == DLL_SLAVE); @@ -136,7 +136,7 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) u8 idle_cnt = is_master ? 0x9 : 0x7; u8 fast_psjp = is_master ? 0x1 : 0x0; - clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0], + clrsetbits32(&ch[chn].phy.shu[0].ca_dll[0], (0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) | (0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4), (phdet_out << 31) | (phdet_in << 30) | @@ -147,11 +147,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) u8 pd_ck_sel = is_master ? 0x1 : 0x0; u8 fastpj_ck_sel = is_master ? 0x0 : 0x1; - clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], + clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1], (0x1 << 2) | (0x1 << 0), (pd_ck_sel << 2) | (fastpj_ck_sel << 0)); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0x1 << 7, (is_master ? 0x1 : 0x0) << 7); struct reg_value regs_bak[] = { @@ -164,86 +164,86 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) regs_bak[i].value = read32(regs_bak[i].addr); for (size_t b = 0; b < 2; b++) - setbits_le32(&ch[chn].phy.b[b].dq[7], + setbits32(&ch[chn].phy.b[b].dq[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); - setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); - setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); + setbits32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0); + setbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); /* 26M */ SET32_BITFIELDS(&ch[chn].phy.misc_cg_ctrl0, MISC_CG_CTRL0_CLK_MEM_SEL, 0); /* MID FINE_TUNE */ - clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27)); - clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27)); - clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27)); - clrbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); + clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27)); + clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27)); + clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27)); + clrbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); /* PLL */ - clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31); - clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + clrbits32(&ch[chn].phy.pll1, 0x1 << 31); + clrbits32(&ch[chn].phy.pll2, 0x1 << 31); /* DLL */ - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], + clrbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], + setbits32(&ch[chn].phy.b[1].dll_fine_tune[2], (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + setbits32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); /* RESETB */ - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); udelay(1); /* MPLL 52M */ - clrsetbits_le32(&ch[chn].phy.shu[0].pll[8], + clrsetbits32(&ch[chn].phy.shu[0].pll[8], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[10], + clrsetbits32(&ch[chn].phy.shu[0].pll[10], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[5], + clrsetbits32(&ch[chn].phy.shu[0].pll[5], (0xffff << 16) | 0x1 << 0, sdm_pcw << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[7], + clrsetbits32(&ch[chn].phy.shu[0].pll[7], (0xffff << 16) | 0x1 << 0, sdm_pcw << 16); - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1); + setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1); + setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1); - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19); - clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], + clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6], (0x3 << 22) | (0x3 << 24) | (0x3 << 28), (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); - clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], + clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6], (0x3 << 22) | (0x3 << 24) | (0x3 << 28), (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], (0x3 << 22) | (0x3 << 24) | (0x3 << 28), (mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28)); /* RESETB */ - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); + setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3); + setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3); udelay(1); /* PLL EN */ - setbits_le32(&ch[chn].phy.pll1, 0x1 << 31); - setbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + setbits32(&ch[chn].phy.pll1, 0x1 << 31); + setbits32(&ch[chn].phy.pll2, 0x1 << 31); udelay(100); /* MIDPI Init 1 */ - setbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); + setbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22)); udelay(1); /* MIDPI Init 2 */ @@ -261,50 +261,50 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) u32 dq6_clear = (0x1 << 26) | (0x1 << 27); u32 dq6_set = (midpi_en << 26) | (midpi_ckdiv4_en << 27); - clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set); - clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set); - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set); + clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set); + clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set); + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set); udelay(1); - clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19, + clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19, (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | ((chn ? 0 : 1) << 19)); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[3], + setbits32(&ch[chn].phy.b[0].dll_fine_tune[3], (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17)); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3], + setbits32(&ch[chn].phy.b[1].dll_fine_tune[3], (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17)); - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + clrbits32(&ch[chn].phy.ca_dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], (0x1 << 10) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11); - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11); + setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11); udelay(2); - setbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4); + setbits32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4); udelay(1); /* DLL */ - setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0); udelay(1); - setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); - setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0); + setbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0); udelay(1); - clrbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); + clrbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21); for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) write32(regs_bak[i].addr, regs_bak[i].value); @@ -312,18 +312,18 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group) cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) { - setbits_le32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0); - setbits_le32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0); - setbits_le32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1); - setbits_le32(&ch[chn].phy.shu[0].pll20, 0x1 << 1); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[14], - 0xffff << 16, 0x0208 << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll20, - 0xffff << 16, 0x0208 << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll[15], - 0xffffffff << 0, delta << 16); - clrsetbits_le32(&ch[chn].phy.shu[0].pll21, - 0xffffffff << 0, delta << 16); + setbits32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0); + setbits32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0); + setbits32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1); + setbits32(&ch[chn].phy.shu[0].pll20, 0x1 << 1); + clrsetbits32(&ch[chn].phy.shu[0].pll[14], + 0xffff << 16, 0x0208 << 16); + clrsetbits32(&ch[chn].phy.shu[0].pll20, + 0xffff << 16, 0x0208 << 16); + clrsetbits32(&ch[chn].phy.shu[0].pll[15], + 0xffffffff << 0, delta << 16); + clrsetbits32(&ch[chn].phy.shu[0].pll21, + 0xffffffff << 0, delta << 16); } } @@ -337,17 +337,17 @@ static void dramc_gating_mode(u8 mode) } for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14); - setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5); + clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14); + setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5); } - clrsetbits_le32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5); - setbits_le32(&ch[0].ao.stbcal, 0x1 << 30); + clrsetbits32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5); + setbits32(&ch[0].ao.stbcal, 0x1 << 30); for (u8 b = 0; b < 2; b++) { - clrbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); udelay(1); - setbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); } } @@ -360,196 +360,196 @@ static void update_initial_settings(u8 freq_group) rx_vref = 0xb; if (operate_fsp == FSP_1) { - setbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); } else { - clrbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + clrbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); } for (size_t b = 0; b < 2; b++) for (size_t r = 0; r < 2; r++) - clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], (0x1 << 23) | (0x1 << 28) | (0x3 << 30)); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0); - - setbits_le32(&ch[0].phy.ca_cmd[3], 0x1 << 10); - setbits_le32(&ch[0].phy.ca_cmd[10], 0x1 << 5); - clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14); - setbits_le32(&ch[0].phy.b[0].dq[3], 0x7 << 5); - setbits_le32(&ch[0].phy.b[1].dq[3], 0x7 << 5); - setbits_le32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7)); - clrbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 1); - clrbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 1); - setbits_le32(&ch[0].phy.b[0].dq[5], 0x1 << 31); - setbits_le32(&ch[0].phy.b[1].dq[5], 0x1 << 31); - setbits_le32(&ch[0].phy.ca_cmd[5], 0x1 << 31); - - clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16); - clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6), + clrbits32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0); + + setbits32(&ch[0].phy.ca_cmd[3], 0x1 << 10); + setbits32(&ch[0].phy.ca_cmd[10], 0x1 << 5); + clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14); + setbits32(&ch[0].phy.b[0].dq[3], 0x7 << 5); + setbits32(&ch[0].phy.b[1].dq[3], 0x7 << 5); + setbits32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7)); + clrbits32(&ch[0].phy.b[0].dq[3], 0x1 << 1); + clrbits32(&ch[0].phy.b[1].dq[3], 0x1 << 1); + setbits32(&ch[0].phy.b[0].dq[5], 0x1 << 31); + setbits32(&ch[0].phy.b[1].dq[5], 0x1 << 31); + setbits32(&ch[0].phy.ca_cmd[5], 0x1 << 31); + + clrsetbits32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16); + clrsetbits32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6), (0x1 << 5) | (0x0 << 6)); - setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 9); - setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 9); - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 9); - clrsetbits_le32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); - clrsetbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0); - clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); - - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 6); - setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 3); - setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 3); - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 3); - setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 5); - setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 5); - setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 5); + setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 9); + setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 9); + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 9); + clrsetbits32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0); + clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 6); + setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 3); + setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 3); + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 3); + setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 5); + setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 5); + setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 5); for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0); - clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); + clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0); + clrsetbits32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8); } - setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); - setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); + setbits32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2)); dramc_gating_mode(1); - setbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 19); - clrbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 18); - clrsetbits_le32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0); - clrsetbits_le32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16), + setbits32(&ch[0].phy.ca_cmd[8], 0x1 << 19); + clrbits32(&ch[0].phy.ca_cmd[8], 0x1 << 18); + clrsetbits32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0); + clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16), (0x2a << 20) | (0x1 << 16)); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); + clrbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8); + clrbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8); + clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8); dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); - clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); - clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); + clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0); + clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0); + clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0); } dramc_set_broadcast(DRAMC_BROADCAST_ON); /* IMP Tracking Init Settings */ - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + clrsetbits32(&ch[0].ao.shu[0].impcal1, (0x7 << 0) | (0x7 << 17) | (0xff << 20) | (0xf << 28), (0x4 << 0) | (0x4 << 17) | (0x10 << 20) | (0x8 << 28)); - setbits_le32(&ch[0].ao.srefctrl, 0xf << 12); - setbits_le32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17); - setbits_le32(&ch[0].ao.shu[0].misc, 0xf << 12); - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[8], + setbits32(&ch[0].ao.srefctrl, 0xf << 12); + setbits32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17); + setbits32(&ch[0].ao.shu[0].misc, 0xf << 12); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[8], (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); - clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[8], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[8], (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[8], + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[8], (0xffff << 0) | (0x1 << 15) | (0x3ff << 22), (0x7fff << 0) | (0x0 << 15) | (0x3ff << 22)); - setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 26); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); - clrsetbits_le32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15), + setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 26); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13)); + clrsetbits32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15), (0x7fff << 0) | (0x1 << 15)); - clrbits_le32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29); - clrbits_le32(&ch[0].ao.write_lev, 0x1 << 2); - setbits_le32(&ch[0].ao.dummy_rd, 0x1 << 24); - clrbits_le32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1)); - setbits_le32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); - setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3)); - - setbits_le32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0); - setbits_le32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0); - setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); - - setbits_le32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26)); - setbits_le32(&ch[0].ao.srefctrl, 0x1 << 22); - clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0); - setbits_le32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12)); - setbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12)); - setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12)); - setbits_le32(&ch[0].ao.stbcal2, 0x1 << 16); - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7], + clrbits32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29); + clrbits32(&ch[0].ao.write_lev, 0x1 << 2); + setbits32(&ch[0].ao.dummy_rd, 0x1 << 24); + clrbits32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1)); + setbits32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); + setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3)); + + setbits32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0); + setbits32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0); + setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); + + setbits32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26)); + setbits32(&ch[0].ao.srefctrl, 0x1 << 22); + clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0); + setbits32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12)); + setbits32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12)); + setbits32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12)); + setbits32(&ch[0].ao.stbcal2, 0x1 << 16); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24), (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24)); - clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[7], + clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24), (0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24)); /* Disable RODT tracking */ - clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0); + clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0); /* Rx Gating tracking settings */ - clrsetbits_le32(&ch[0].ao.shu[0].dqsg, + clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12)); - clrbits_le32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15)); - clrbits_le32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15)); - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, + clrbits32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15)); + clrbits32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15)); + clrsetbits32(&ch[0].ao.shu[0].stbcal, (0x7 << 4) | (0x1 << 8), (0x1 << 4) | (0x1 << 8)); - clrsetbits_le32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8); - clrsetbits_le32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8); - clrbits_le32(&ch[0].phy.ca_cmd[10], 0xff << 8); + clrsetbits32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8); + clrsetbits32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8); + clrbits32(&ch[0].phy.ca_cmd[10], 0xff << 8); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24); + setbits32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24); + setbits32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24); /* Enable WDQS */ - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dll[1], + clrsetbits32(&ch[0].phy.shu[0].b[0].dll[1], (0x1 << 10) | (0x1 << 16) | (0x1 << 17), (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17)); - clrsetbits_le32(&ch[0].phy.shu[0].b[1].dll[1], + clrsetbits32(&ch[0].phy.shu[0].b[1].dll[1], (0x1 << 10) | (0x1 << 16) | (0x1 << 17), (0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17)); - setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - setbits_le32(&ch[0].ao.drsctrl, 0x1 << 19); - setbits_le32(&ch[0].ao.refctrl0, 0x1 << 28); - setbits_le32(&ch[0].ao.zqcs, 0x1 << 19); - setbits_le32(&ch[0].ao.dummy_rd, 0x3 << 26); - setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 8); - clrsetbits_le32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24); - setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 27); - setbits_le32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20); - setbits_le32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20); - setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20); - clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 27); - setbits_le32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8); - setbits_le32(&ch[0].ao.clkctrl, 0x1 << 7); - setbits_le32(&ch[0].ao.refctrl1, 0x1 << 7); - clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26), + setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].ao.drsctrl, 0x1 << 19); + setbits32(&ch[0].ao.refctrl0, 0x1 << 28); + setbits32(&ch[0].ao.zqcs, 0x1 << 19); + setbits32(&ch[0].ao.dummy_rd, 0x3 << 26); + setbits32(&ch[0].ao.shuctrl2, 0x1 << 8); + clrsetbits32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24); + setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 27); + setbits32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20); + setbits32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20); + setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 27); + setbits32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8); + setbits32(&ch[0].ao.clkctrl, 0x1 << 7); + setbits32(&ch[0].ao.refctrl1, 0x1 << 7); + clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26), (0x0 << 2) | (0x3 << 6) | (0x3 << 26)); - setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10)); - clrbits_le32(&ch[0].ao.stbcal2, 0xf << 4); - clrbits_le32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19); + setbits32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10)); + clrbits32(&ch[0].ao.stbcal2, 0xf << 4); + clrbits32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19); - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22); - clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), + setbits32(&ch[0].ao.ckectrl, 0x1 << 22); + clrsetbits32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26), (0x1 << 31) | (0xa << 21) | (0xa << 26)); - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23); - clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); + setbits32(&ch[0].ao.ckectrl, 0x1 << 23); + clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31); } static void dramc_power_on_sequence(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); + clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); dramc_cke_fix_onoff(CHANNEL_A, false, true); dramc_cke_fix_onoff(CHANNEL_B, false, true); udelay(200); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); udelay(2000); dramc_cke_fix_onoff(CHANNEL_A, true, false); @@ -571,22 +571,22 @@ static void ddr_phy_reserved_rg_setting(u8 freq_group) /* fine tune */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6, + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6, (0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) | (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1], + clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1], (0xf << 9) | (0x1f << 16) | (0x7ff << 21), (0x1 << 8) | (0x7 << 13) | (0x4 << 16)); for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[6], + clrsetbits32(&ch[chn].phy.shu[0].b[b].dq[6], (0x1f << 6) | (0x3f << 11) | (0x7 << 19), (0x1 << 6) | (hyst_sel << 8) | (midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20)); - clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dll[1], + clrsetbits32(&ch[chn].phy.shu[0].b[b].dll[1], (0x3 << 8) | (0x3 << 11) | (0x7 << 14) | (0x3fff << 18), (0x1 << 10) | (0x1 << 13) | (0x1 << 17)); } @@ -603,12 +603,12 @@ static void dramc_duty_set_clk_delay(u8 chn, s8 clkDelay) revb1 = dlyb ? 1 : 0; for (u8 r = 0; r < RANK_MAX; r++) { - clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1], + clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1], (0xf << 24) | (0xf << 28), (dly << 24) | (dly << 28)); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0], + clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0], (0xf << 24) | (0xf << 28), (dlyb << 24) | (dlyb << 28)); } - clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[3], + clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[3], (0x3 << 8), (revb0 << 8) | (revb1 << 9)); } @@ -625,11 +625,11 @@ static void dramc_duty_set_dqs_delay(u8 chn, const s8 *s_dqsDelay) dlyb = (dqsDelay < 0) ? 0 : dqsDelay; revb0 = dly ? 1 : 0; revb1 = dlyb ? 1 : 0; - clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1], + clrsetbits32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1], (0xf << 24) | (0xf << 28) | (0xf << 16) | (0xf << 20), (dly << 24) | (dly << 28) | (dlyb << 16) | (dlyb << 20)); } - clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dll[1], + clrsetbits32(&ch[chn].phy.shu[0].b[0].dll[1], 0x3 << 8, (revb0 << 8) | (revb1 << 9)); } @@ -709,7 +709,7 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank) for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++) regs_bak[i].value = read32(regs_bak[i].addr); - setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); dramc_cke_fix_onoff(chn, true, false); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); @@ -794,7 +794,7 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) for (chn = 0; chn < CHANNEL_MAX; chn++) { for (rank = 0; rank < 2; rank++) { - clrsetbits_le32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24); + clrsetbits32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24); dramc_zq_calibration(chn, rank); @@ -827,21 +827,21 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr) dramc_mode_reg_write(chn, 0xd, MR13Value); } - clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr13, + clrsetbits32(&ch[chn].ao.shu[0].hwset_mr13, (0x1fff << 0) | (0xff << 16), (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].hwset_vrcg, + clrsetbits32(&ch[chn].ao.shu[0].hwset_vrcg, (0x1fff << 0) | (0xff << 16), (13 << 0) | ((MR13Value | (0x1 << 3)) << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr2, + clrsetbits32(&ch[chn].ao.shu[0].hwset_mr2, (0x1fff << 0) | (0xff << 16), (2 << 0) | (MR02Value[operate_fsp] << 16)); } mr->MR13Value = MR13Value; - clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); - clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); + clrsetbits32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24); + clrsetbits32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24); dramc_set_broadcast(broadcast_bak); } @@ -851,7 +851,7 @@ static void auto_refresh_cke_off(void) dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (u8 chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.refctrl0, 0x1 << 29); + setbits32(&ch[chn].ao.refctrl0, 0x1 << 29); udelay(3); cke_fix_onoff(CKE_FIXOFF, CHANNEL_A); @@ -862,57 +862,57 @@ static void auto_refresh_cke_off(void) static void dramc_setting_DDR1600(void) { - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), (0x0 << 20) | (0x0 << 24) | (0x2 << 28)); - clrbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24); - clrbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30)); + clrbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24); + clrbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30)); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600); - clrsetbits_le32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600); + clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), (0x0 << 29) | (0x1 << 31)); - clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0); + clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0); for (size_t rank = 0; rank < 2; rank++) { int value = ((rank == 0) ? 0x1a : 0x1e); - clrbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune, + clrbits32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8)); + clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (value << 0) | (value << 8) | (value << 16) | (value << 24)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x2 << 8) | (0x2 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x2 << 8) | (0x2 << 12) | (0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, _SELPH_DQS_BITS(0x1, 0x7)); } - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x0 << 2) | (0x3 << 8)); - clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); + clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20); - clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x2 << 4) | (0x0 << 7) | (0x0 << 13)); - clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); - clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); + clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20); + clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { int value = ((r == 0) ? 0x1a : 0x26); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (value << 8) | (value << 16)); } @@ -920,65 +920,65 @@ static void dramc_setting_DDR1600(void) static void dramc_setting_DDR2400(void) { - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), (0x2 << 20) | (0x2 << 24) | (0x4 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24); - setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); + clrsetbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24); + setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400); - clrsetbits_le32(&ch[0].ao.shu[0].wodt, + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400); + clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31), (0x1 << 29) | (0x0 << 31)); - clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0); + clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0); for (size_t rank = 0; rank < 2; rank++) { int value = ((rank == 0) ? 0x19 : 0x1f); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8), (value << 0) | (value << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune, + clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x3 << 8) | (0x3 << 12) | (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x3 << 8) | (0x3 << 12) | (0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, _SELPH_DQS_BITS(0x2, 0x0)); } - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8)); - clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), + clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13), (0x1 << 4) | (0x1 << 7) | (0x1 << 13)); - clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&ch[0].phy.b[1].dq[7], + clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13)); for (size_t r = 0; r < 2; r++) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16)); } } static void dramc_setting_DDR3600(void) { - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600); } static void dramc_setting(const struct sdram_params *params, u8 freq_group, @@ -990,158 +990,158 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1)); + setbits32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1)); dramc_set_broadcast(DRAMC_BROADCAST_ON); - setbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0); + setbits32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0); /* 26M */ - clrbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4); - clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 17); + clrbits32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4); + clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 17); - clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); + clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); write32(&ch[0].phy.misc_spm_ctrl2, 0x0); write32(&ch[0].phy.misc_spm_ctrl0, 0x0); write32(&ch[0].phy.misc_cg_ctrl2, 0x6003bf); write32(&ch[0].phy.misc_cg_ctrl4, 0x333f3f00); - setbits_le32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1)); - clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0); + setbits32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1)); + clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0); for (size_t b = 0; b <= 2; b += 2) - clrsetbits_le32(&ch[0].phy.shu[0].pll[4 + b], + clrsetbits32(&ch[0].phy.shu[0].pll[4 + b], (0x3 << 18) | (0x3 << 24) | (0x3 << 26), (0x2 << 18) | (0x1 << 24) | (0x1 << 26)); - clrbits_le32(&ch[0].phy.shu[0].pll[14], 0x1 << 1); - clrbits_le32(&ch[0].phy.shu[0].pll20, 0x1 << 1); - clrbits_le32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20)); + clrbits32(&ch[0].phy.shu[0].pll[14], 0x1 << 1); + clrbits32(&ch[0].phy.shu[0].pll20, 0x1 << 1); + clrbits32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20)); for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20)); + clrbits32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20)); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28); - clrbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 28); + clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28); + clrbits32(&ch[0].phy.ca_cmd[10], 0x7 << 28); - setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); - setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); - setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9); - setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9); + setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); + setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); + setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9); + setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9); for (size_t b = 0; b < 2; b++) { for (size_t r = 0; r < 2; r++) - setbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29); - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20); + setbits32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29); + clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20); for (size_t r = 0; r < 2; r++) { - clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[1], + clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[1], (0xffff << 0) | (0xffff << 16), (0x2 << 0) | (0x2 << 16)); - clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[2], (0x1 << 23) | (0x1 << 28) | (0x3 << 30), (0x1 << 23) | (0x1 << 28) | (0x2 << 30)); } } - clrbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); - clrbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); + clrbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28); + clrbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28); for (size_t b = 0; b < 2; b++) { - setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 0); + setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 0); for (size_t r = 0; r < 2; r++) - clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x1f << 8) | (0x1f << 16)); - clrsetbits_le32(&ch[0].phy.b[b].dq[4], + clrsetbits32(&ch[0].phy.b[b].dq[4], (0x7f << 0) | (0x7f << 8), (0x10 << 0) | (0x10 << 8)); - clrsetbits_le32(&ch[0].phy.b[b].dq[5], + clrsetbits32(&ch[0].phy.b[b].dq[5], (0xff << 0) | (0x3f << 8) | (0x1 << 16) | (0xf << 20) | (0x1 << 24), (0x10 << 0) | (0xe << 8) | (0x1 << 16) | (0x1 << 20) | (0x0 << 24)); - clrsetbits_le32(&ch[0].phy.b[b].dq[6], + clrsetbits32(&ch[0].phy.b[b].dq[6], (0x1 << 4) | (0x1 << 7) | (0x1 << 12) | (0x3 << 14) | (0xf << 16) | (0x1 << 24), (0x0 << 4) | (0x1 << 7) | (0x1 << 12) | (0x0 << 14) | (0x3 << 16) | (0x1 << 24)); - clrsetbits_le32(&ch[0].phy.b[b].dq[5], + clrsetbits32(&ch[0].phy.b[b].dq[5], (0xff << 0) | (0x1 << 25), (0x0 << 0) | (0x1 << 25)); } - setbits_le32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7)); - clrsetbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), + setbits32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7)); + clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16), (0x0 << 6) | (0x0 << 14) | (0x0 << 16)); - clrbits_le32(&ch[0].phy.pll3, 0x1 < 0); - setbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 3); - setbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 3); + clrbits32(&ch[0].phy.pll3, 0x1 < 0); + setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3); + setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3); udelay(1); - clrsetbits_le32(&ch[0].phy.shu[0].pll[8], + clrsetbits32(&ch[0].phy.shu[0].pll[8], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); udelay(1); - clrbits_le32(&ch[0].phy.shu[0].pll[9], + clrbits32(&ch[0].phy.shu[0].pll[9], (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16)); - clrbits_le32(&ch[0].phy.shu[0].pll[11], + clrbits32(&ch[0].phy.shu[0].pll[11], (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16)); udelay(1); - clrsetbits_le32(&ch[0].phy.shu[0].pll[10], + clrsetbits32(&ch[0].phy.shu[0].pll[10], (0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18)); udelay(1); /* PLL EN */ /* MID FINE_TUNE Init 1 */ - clrsetbits_le32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18); + clrsetbits32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18); udelay(1); - clrsetbits_le32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0); + clrsetbits32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0); udelay(1); - setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); + setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21); for (size_t b = 0; b < 2; b++) - setbits_le32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); - setbits_le32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); + setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10)); + setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0], + clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0], (0x1 << 4) | (0x3 << 9) | (0xf << 12) | (0xf << 16) | (0xf << 20) | (0x1 << 30), (0x0 << 4) | (0x3 << 9) | (0x8 << 12) | (0x7 << 16) | (0x7 << 20) | (0x1 << 30)); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[0], + clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[0], (0x1 << 4) | (0x7 << 12) | (0x1 << 20), (0x1 << 4) | (0x4 << 12) | (0x1 << 20)); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6); - clrsetbits_le32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6); + clrsetbits32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6); dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); + clrsetbits32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6); dramc_set_broadcast(DRAMC_BROADCAST_OFF); for (chn = 0; chn < CHANNEL_MAX; chn++) - clrsetbits_le32(&ch[chn].phy.misc_shu_opt, + clrsetbits32(&ch[chn].phy.misc_shu_opt, (0x1 << 0) | (0x3 << 2) | (0x1 << 8) | (0x3 << 10) | (0x1 << 16) | (0x3 << 18), (0x1 << 0) | (0x2 << 2) | (0x1 << 8) | (0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18)); udelay(9); - clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); - clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); + clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2); + clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0); dramc_set_broadcast(DRAMC_BROADCAST_ON); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1], + clrsetbits32(&ch[0].phy.shu[0].b[b].dll[1], (0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2)); udelay(1); - clrbits_le32(&ch[0].phy.pll2, 0x1 << 31); - clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf); + clrbits32(&ch[0].phy.pll2, 0x1 << 31); + clrsetbits32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf); udelay(1); dramc_set_broadcast(DRAMC_BROADCAST_OFF); @@ -1150,241 +1150,241 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, ddr_phy_pll_setting(chn, freq_group); dramc_set_broadcast(DRAMC_BROADCAST_ON); - setbits_le32(&ch[0].ao.drsctrl, 0x1 << 29); + setbits32(&ch[0].ao.drsctrl, 0x1 << 29); /* Set Run time MRR CKE fix to 1 in tMRRI old mode * to avoid no ACK from precharge all */ - setbits_le32(&ch[0].ao.ckectrl, 0x1 << 27); - clrsetbits_le32(&ch[0].ao.dramctrl, + setbits32(&ch[0].ao.ckectrl, 0x1 << 27); + clrsetbits32(&ch[0].ao.dramctrl, (0x1 << 15) | (0x1 << 17) | (0x1 << 23), (0x0 << 15) | (0x1 << 17) | (0x1 << 23)); - setbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); - setbits_le32(&ch[0].phy.b[0].dq[9], 0x1 << 4); - setbits_le32(&ch[0].phy.b[1].dq[9], 0x1 << 4); + setbits32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10)); + setbits32(&ch[0].phy.b[0].dq[9], 0x1 << 4); + setbits32(&ch[0].phy.b[1].dq[9], 0x1 << 4); - clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien, (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), (0xf << 0) | (0xf << 8) | (0xf << 16) | (0xf << 24)); - clrsetbits_le32(&ch[0].ao.stbcal1, + clrsetbits32(&ch[0].ao.stbcal1, (0x1 << 4) | (0x1 << 8) | (0x1 << 12), (0x1 << 4) | (0x1 << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 3) | (0xf << 8) | (0x1 << 21) | (0x1 << 31), (0x1 << 3) | (0x6 << 8) | (0x1 << 21) | (0x1 << 31)); for (size_t i = 0; i < 4; i++) { - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 0) | (0x1f << 5) | (0x1f << 10) | (0x1f << 15) | (0x1f << 20) | (0x1f << 25), (0xa << 0) | (0xa << 5) | (0xa << 10) | (0xa << 15) | (0xa << 20) | (0xa << 25)); } - clrsetbits_le32(&ch[0].ao.shuctrl2, + clrsetbits32(&ch[0].ao.shuctrl2, (0x3f << 0) | (0x1 << 12) | (0x1 << 14) | (0x1 << 15) | (0xff << 16) | (0x1 << 24), (0xa << 0) | (0x1 << 12) | (0x1 << 14) | (0x1 << 15) | (0x1 << 16) | (0x0 << 24)); - setbits_le32(&ch[0].ao.dvfsdll, 0x1 << 0); - setbits_le32(&ch[0].ao.ddrconf0, + setbits32(&ch[0].ao.dvfsdll, 0x1 << 0); + setbits32(&ch[0].ao.ddrconf0, (0x1 << 12) | (0x1 << 15) | (0x1 << 20) | (0x1 << 26)); - setbits_le32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28)); - clrbits_le32(&ch[0].ao.stbcal2, 0x1 << 29); - setbits_le32(&ch[0].ao.clkar, 0x1 << 19); + setbits32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28)); + clrbits32(&ch[0].ao.stbcal2, 0x1 << 29); + setbits32(&ch[0].ao.clkar, 0x1 << 19); for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20); - clrsetbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20); - setbits_le32(&ch[0].phy.misc_ctrl0, + clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20); + clrsetbits32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20); + setbits32(&ch[0].phy.misc_ctrl0, (0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31)); - setbits_le32(&ch[0].phy.misc_ctrl1, + setbits32(&ch[0].phy.misc_ctrl1, (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24)); - clrsetbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); - clrsetbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); - clrsetbits_le32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); - clrbits_le32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6)); - clrbits_le32(&ch[0].phy.b[0].dq[7], 0x1 << 6); - clrbits_le32(&ch[0].phy.b[1].dq[7], 0x1 << 6); - - clrsetbits_le32(&ch[0].ao.shu[0].conf[0], + clrsetbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24); + clrsetbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24); + clrsetbits32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24); + clrbits32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6)); + clrbits32(&ch[0].phy.b[0].dq[7], 0x1 << 6); + clrbits32(&ch[0].phy.b[1].dq[7], 0x1 << 6); + + clrsetbits32(&ch[0].ao.shu[0].conf[0], (0x3f << 0) | (0x1 << 7) | (0xf << 12) | (0x1 << 24) | (0x1 << 29) | (0x3 << 30), (0x3f << 0) | (0x1 << 7) | (0x1 << 12) | (0x1 << 24) | (0x1 << 29) | (0x2 << 30)); - clrsetbits_le32(&ch[0].ao.shu[0].odtctrl, + clrsetbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 1) | (0x7f << 16) | (0x1 << 30) | (0x1 << 31), (0x1 << 0) | (0x1 << 1) | (0x1 << 16) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15); - clrsetbits_le32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24); - clrbits_le32(&ch[0].ao.shu[0].selph_ca1, + clrsetbits32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24); + clrbits32(&ch[0].ao.shu[0].selph_ca1, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].selph_ca2, + clrsetbits32(&ch[0].ao.shu[0].selph_ca2, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 16) | (0x7 << 24), (0x0 << 0) | (0x0 << 4) | (0x0 << 8) | (0x7 << 16) | (0x0 << 24)); - clrbits_le32(&ch[0].ao.shu[0].selph_ca3, + clrbits32(&ch[0].ao.shu[0].selph_ca3, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); - clrbits_le32(&ch[0].ao.shu[0].selph_ca4, + clrbits32(&ch[0].ao.shu[0].selph_ca4, (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); - clrbits_le32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); - clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); + clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); for (size_t rank = 0; rank < 2; rank++) { - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1], 0x77777777, _SELPH_DQS_BITS(0x3, 0x3)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, _SELPH_DQS_BITS(0x6, 0x2)); } for (int b = 0; b < 2; b++) { - clrsetbits_le32(&ch[0].phy.shu[0].rk[0].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[0].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x1a << 8) | (0x1a << 16)); - clrsetbits_le32(&ch[0].phy.shu[0].rk[1].b[b].dq[7], + clrsetbits32(&ch[0].phy.shu[0].rk[1].b[b].dq[7], (0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16)); } udelay(1); for (size_t b = 0; b < 2; b++) { - setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5); - clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14); + setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5); + clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14); } - setbits_le32(&ch[0].ao.stbcal, 0x1 << 31); - clrsetbits_le32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24); - clrsetbits_le32(&ch[0].ao.shu[0].ckectrl, + setbits32(&ch[0].ao.stbcal, 0x1 << 31); + clrsetbits32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24); + clrsetbits32(&ch[0].ao.shu[0].ckectrl, (0x3 << 24) | (0x3 << 28), (0x3 << 24) | (0x3 << 28)); - setbits_le32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31)); - setbits_le32(&ch[0].ao.rkcfg, 0x1 << 2); - clrsetbits_le32(&ch[0].ao.shu[0].conf[2], + setbits32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31)); + setbits32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31)); + setbits32(&ch[0].ao.rkcfg, 0x1 << 2); + clrsetbits32(&ch[0].ao.shu[0].conf[2], (0x7 << 16) | (0x1 << 28), (0x7 << 16) | (0x1 << 28)); - clrsetbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26); - clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0); + clrsetbits32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26); + clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0); - setbits_le32(&ch[0].ao.shuctrl, 0x1 << 16); - clrbits_le32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6)); - clrsetbits_le32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23), + setbits32(&ch[0].ao.shuctrl, 0x1 << 16); + clrbits32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6)); + clrsetbits32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23), (0x1 << 15) | (0x0 << 23)); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 9); - setbits_le32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31)); - setbits_le32(&ch[0].ao.perfctl0, + clrbits32(&ch[0].ao.dramctrl, 0x1 << 9); + setbits32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31)); + setbits32(&ch[0].ao.perfctl0, (0x1 << 0) | (0x1 << 1) | (0x1 << 4) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10) | (0x1 << 11) | (0x1 << 14) | (0x1 << 17)); - clrsetbits_le32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0); - clrsetbits_le32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3)); - setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8); - setbits_le32(&ch[0].ao.clkctrl, 0x1 << 29); - clrsetbits_le32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12)); - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), + clrsetbits32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0); + clrsetbits32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3)); + setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8); + setbits32(&ch[0].ao.clkctrl, 0x1 << 29); + clrsetbits32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12)); + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28), (0x4 << 20) | (0x4 << 24) | (0x6 << 28)); udelay(2); - clrsetbits_le32(&ch[0].ao.shu[0].rk[0].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien, (0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien, + clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien, (0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24), (0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24)); - setbits_le32(&ch[0].ao.dramctrl, 0x1 << 19); - clrsetbits_le32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0); + setbits32(&ch[0].ao.dramctrl, 0x1 << 19); + clrsetbits32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0); udelay(1); - clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16); - setbits_le32(&ch[0].ao.refctrl0, 0x1 << 30); - setbits_le32(&ch[0].ao.srefctrl, 0x1 << 30); - setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); - setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30); - setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0); - clrsetbits_le32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16)); - setbits_le32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11)); - clrsetbits_le32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4); - clrsetbits_le32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4); - clrsetbits_le32(&ch[0].ao.test2_3, + clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16); + setbits32(&ch[0].ao.refctrl0, 0x1 << 30); + setbits32(&ch[0].ao.srefctrl, 0x1 << 30); + setbits32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30); + setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0); + clrsetbits32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16)); + setbits32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11)); + clrsetbits32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4); + clrsetbits32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4); + clrsetbits32(&ch[0].ao.test2_3, (0x1 << 7) | (0x7 << 8) | (0x1 << 28), (0x1 << 7) | (0x4 << 8) | (0x1 << 28)); - clrbits_le32(&ch[0].ao.rstmask, 0x1 << 29); - clrbits_le32(&ch[0].ao.rstmask, 0x1 << 30); + clrbits32(&ch[0].ao.rstmask, 0x1 << 29); + clrbits32(&ch[0].ao.rstmask, 0x1 << 30); udelay(1); - clrsetbits_le32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); + clrsetbits32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4)); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); - clrsetbits_le32(&ch[0].ao.perfctl0, + clrbits32(&ch[0].ao.dramctrl, 0x1 << 0); + clrsetbits32(&ch[0].ao.perfctl0, (0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19)); - setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28); - clrbits_le32(&ch[0].ao.rstmask, 0x1 << 28); - setbits_le32(&ch[0].ao.rkcfg, 0x1 << 11); - setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17); - setbits_le32(&ch[0].ao.eyescan, 0x1 << 2); - setbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 29); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20); + setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28); + clrbits32(&ch[0].ao.rstmask, 0x1 << 28); + setbits32(&ch[0].ao.rkcfg, 0x1 << 11); + setbits32(&ch[0].ao.mpc_option, 0x1 << 17); + setbits32(&ch[0].ao.eyescan, 0x1 << 2); + setbits32(&ch[0].ao.shu[0].wodt, 0x1 << 29); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7); + clrsetbits32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20); for (size_t r = 0; r < 2; r++) { - clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[0], + clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[0], (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[1], + clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[1], (0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4)); } udelay(5); - clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16); - clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16); - clrsetbits_le32(&ch[0].ao.stbcal, + clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16); + clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16); + clrsetbits32(&ch[0].ao.stbcal, (0x1 << 0) | (0x1 << 22) | (0x1 << 24) | (0x1 << 26) | (0x1 << 27), (0x1 << 0) | (0x0 << 22) | (0x0 << 24) | (0x1 << 26) | (0x1 << 27)); - setbits_le32(&ch[0].ao.stbcal1, 0x1 << 6); - clrsetbits_le32(&ch[0].ao.shu[0].dqsg, + setbits32(&ch[0].ao.stbcal1, 0x1 << 6); + clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12)); - clrbits_le32(&ch[0].phy.misc_ctrl0, 0xf << 0); - setbits_le32(&ch[0].ao.shu[0].stbcal, 0x1 << 8); - setbits_le32(&ch[0].ao.stbcal, 0x1 << 17); - clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14); - clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14); - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); + clrbits32(&ch[0].phy.misc_ctrl0, 0xf << 0); + setbits32(&ch[0].ao.shu[0].stbcal, 0x1 << 8); + setbits32(&ch[0].ao.stbcal, 0x1 << 17); + clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14); + clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14); + clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4); if (freq_group == LP4X_DDR1600) - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0); + clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0); else - clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); - setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); - setbits_le32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27)); - clrbits_le32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26)); - clrsetbits_le32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4); + clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0); + setbits32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5)); + setbits32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27)); + clrbits32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26)); + clrsetbits32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4); udelay(12); - clrsetbits_le32(&ch[0].ao.shu[0].rankctl, + clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 24) | (0xf << 28), (0x4 << 24) | 0x6 << 28); - clrbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 31); - clrsetbits_le32(&ch[0].ao.shu[0].rk[0].fine_tune, + clrbits32(&ch[0].ao.shu[0].wodt, 0x1 << 31); + clrsetbits32(&ch[0].ao.shu[0].rk[0].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x1a << 0) | (0x1a << 8) | (0x1a << 16) | (0x1a << 24)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[1].fine_tune, + clrsetbits32(&ch[0].ao.shu[0].rk[1].fine_tune, (0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24), (0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24)); for (u8 rank = 0; rank < 2; rank++) { - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2], (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28)); - clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3], (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28), (0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28)); } - clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, + clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8) | (0x1 << 14) | (0x3 << 24), (0x1 << 2) | (0x5 << 8) | (0x0 << 14) | (0x1 << 24)); - setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13)); - setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); - clrbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); + setbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13)); + setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13)); + clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0); switch (freq_group) { case LP4X_DDR1600: @@ -1407,28 +1407,28 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group, update_initial_settings(freq_group); dramc_sw_impedance_save_reg(freq_group, impedance); - clrbits_le32(&ch[0].ao.test2_4, 0x1 << 17); - clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); + clrbits32(&ch[0].ao.test2_4, 0x1 << 17); + clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0); udelay(1); - setbits_le32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18)); - setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25)); - setbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); - setbits_le32(&ch[0].ao.dramctrl, 0x1 << 26); - clrsetbits_le32(&ch[0].ao.dummy_rd, + setbits32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18)); + setbits32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25)); + setbits32(&ch[0].ao.refctrl0, 0x1 << 29); + setbits32(&ch[0].ao.dramctrl, 0x1 << 26); + clrsetbits32(&ch[0].ao.dummy_rd, (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x3 << 16) | (0x1 << 22), (0x1 << 4) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x2 << 16) | (0x1 << 22)); - clrsetbits_le32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0); + clrsetbits32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28); + clrbits32(&ch[0].ao.dramctrl, 0x1 << 0); udelay(1); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17)); - setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 12); - clrsetbits_le32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17)); - clrbits_le32(&ch[1].ao.shuctrl2, 0x1 << 12); + clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17)); + setbits32(&ch[0].ao.shuctrl2, 0x1 << 12); + clrsetbits32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17)); + clrbits32(&ch[1].ao.shuctrl2, 0x1 << 12); } struct ac_time { @@ -1651,33 +1651,33 @@ static void ddr_update_ac_timing(u8 freq_group) } for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].ao.shu[0].actim[0], + clrsetbits32(&ch[chn].ao.shu[0].actim[0], (0xf << 24) | (0x7 << 16) | (0x1f << 8) | (0xf << 0), (ac_t.trcd << 24) | (ac_t.trrd << 16) | (ac_t.twr << 8) | (ac_t.twtr << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[1], + clrsetbits32(&ch[chn].ao.shu[0].actim[1], (0x1f << 24) | (0xf << 16) | (0xf << 8) | (0x7 << 0), (ac_t.trc << 24) | (ac_t.tras << 16) | (ac_t.trp << 8) | (ac_t.trpab << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[2], + clrsetbits32(&ch[chn].ao.shu[0].actim[2], (0x1f << 24) | (0xf << 16) | (0x7 << 8) | (0x7 << 0), (ac_t.tfaw << 24) | (trtw << 16) | (ac_t.trtp << 8) | (ac_t.txp << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + clrsetbits32(&ch[chn].ao.shu[0].actim[3], (0xff << 16) | (0xff << 24) | (0xff << 0), (ac_t.trfc << 16) | (ac_t.refcnt << 24) | (ac_t.trfcpb << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], + clrsetbits32(&ch[chn].ao.shu[0].actim[4], (0xff << 24) | (0xff << 16) | (0x3ff << 0), (ac_t.tzqcs << 24) | (ac_t.refcnt_fr_clk << 16) | (ac_t.txrefcnt << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[5], + clrsetbits32(&ch[chn].ao.shu[0].actim[5], (0xf << 24) | (0x1f << 8) | (0x1f << 0), (tmrr2w << 24) | (ac_t.twtpd << 8) | (ac_t.trtpd << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt, + clrsetbits32(&ch[chn].ao.shu[0].actim_xrt, (0xf << 24) | (0x7 << 16) | (0xf << 8) | (0x1f << 0), (ac_t.xrtw2w << 24) | (ac_t.xrtw2r << 16) | (ac_t.xrtr2w << 8) | (ac_t.xrtr2r << 0)); - clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t, (0x1 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15) | (0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) | @@ -1690,45 +1690,45 @@ static void ddr_update_ac_timing(u8 freq_group) (ac_t.trcd_05T << 6) | (ac_t.trtp_05T << 5) | (ac_t.txp_05T << 4) | (ac_t.trfc_05T << 2) | (ac_t.trfcpb_05T << 1) | (ac_t.trc_05T << 0)); - clrsetbits_le32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20), + clrsetbits32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20), (ac_t.r_dmcatrain_intv << 24) | (0x0 << 20)); /* DQSINCTL related */ - clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0, + clrsetbits32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0, ac_t.dqsinctl << 0); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0, + clrsetbits32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0, ac_t.dqsinctl << 0); - clrsetbits_le32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4, + clrsetbits32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4, ac_t.dqsinctl << 4); /* DATLAT related, tREFBW */ - clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], + clrsetbits32(&ch[chn].ao.shu[0].conf[1], (0x1f << 0) | (0x1f << 8) | (0x1f << 26) | (0x3ff << 16), (ac_t.datlat << 0) | (new_datlat << 8) | (new_datlat << 26) | (0x0 << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].conf[2], + clrsetbits32(&ch[chn].ao.shu[0].conf[2], (0xff << 8), ac_t.r_dmfspchg_prdcnt << 8); - clrsetbits_le32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6), + clrsetbits32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6), (ac_t.r_dmmrw_intv << 13) | (ac_t.zqlat2 << 6)); /* CKEPRD - CKE pulse width */ - clrsetbits_le32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20); + clrsetbits32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20); /* CKELCKCNT: Valid clock requirement after CKE input low */ - clrsetbits_le32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24); + clrsetbits32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24); temp = ((read32(&ch[chn].ao.shu[0].rankctl) & 0x00f00000) >> 20) & 0xf; - clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0); + clrsetbits32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0); - clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + clrsetbits32(&ch[chn].ao.shu[0].rankctl, (0xf << 16) | (0xf << 12) | (0xf << 8), (root << 16) | (tx_rank_inctl << 12) | (tx_dly << 8)); } u8 dram_cbt_mode = 0; - clrsetbits_le32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10); - clrsetbits_le32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode); - clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); + clrsetbits32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10); + clrsetbits32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode); + clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode); } void dramc_init(const struct sdram_params *params, u8 freq_group, diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index eb30381953..1eb86f406f 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -48,7 +48,7 @@ static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) } } - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); } void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, @@ -60,29 +60,29 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); - clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); + clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0); write32(&ch[0].phy.misc_spm_ctrl2, 0x0); write32(&ch[0].phy.misc_spm_ctrl0, 0x0); - clrbits_le32(&ch[0].ao.impcal, 0x1 << 31); + clrbits32(&ch[0].ao.impcal, 0x1 << 31); impcal_bak = read32(&ch[0].ao.impcal); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP); - clrbits_le32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6); - clrsetbits_le32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24); - clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); + clrbits32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6); + clrsetbits32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24); + clrsetbits32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4); udelay(1); dramc_dbg("impedance: K DRVP\n"); - setbits_le32(&ch[0].ao.impcal, 0x1 << 23); - setbits_le32(&ch[0].ao.impcal, 0x1 << 22); - clrbits_le32(&ch[0].ao.impcal, 0x1 << 21); - clrbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); + setbits32(&ch[0].ao.impcal, 0x1 << 23); + setbits32(&ch[0].ao.impcal, 0x1 << 22); + clrbits32(&ch[0].ao.impcal, 0x1 << 21); + clrbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { impx_drv = (impx_drv == 16) ? 29 : impx_drv; - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4, impx_drv << 4); udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> @@ -100,17 +100,17 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, dramc_dbg("impedance: K ODTN\n"); dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN); - clrbits_le32(&ch[0].ao.impcal, 0x1 << 22); + clrbits32(&ch[0].ao.impcal, 0x1 << 22); if (term == ODT_ON) - setbits_le32(&ch[0].ao.impcal, 0x1 << 21); - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, + setbits32(&ch[0].ao.impcal, 0x1 << 21); + clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11, DRVP_result << 4 | 0x1f << 11); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3); for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) { impx_drv = (impx_drv == 16) ? 29 : impx_drv; - clrsetbits_le32(&ch[0].ao.shu[0].impcal1, + clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 11, impx_drv << 11); udelay(1); imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> @@ -163,31 +163,31 @@ void dramc_sw_impedance_save_reg(u8 freq_group, sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3); dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); /* DQ */ - clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), + clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][0] << 5) | (sw_impedance[dq_term][1] << 0)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[1], + clrsetbits32(&ch[0].ao.shu[0].drving[1], (0x1f << 25) | (0x1f << 20) | (1 << 31), (sw_impedance[dq_term][0] << 25) | (sw_impedance[dq_term][1] << 20) | (!dq_term << 31)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0), + clrsetbits32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0), (sw_impedance[dq_term][2] << 5) | (sw_impedance[dq_term][3] << 0)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20), + clrsetbits32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20), (sw_impedance[dq_term][2] << 25) | (sw_impedance[dq_term][3] << 20)); /* DQS */ for (u8 i = 0; i <= 2; i += 2) { - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 25) | (0x1f << 20), (sw_impedance[dq_term][i] << 25) | (sw_impedance[dq_term][i + 1] << 20)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 15) | (0x1f << 10), (sw_impedance[dq_term][i] << 15) | (sw_impedance[dq_term][i + 1] << 10)); @@ -195,19 +195,19 @@ void dramc_sw_impedance_save_reg(u8 freq_group, /* CMD & CLK */ for (u8 i = 1; i <= 3; i += 2) { - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 15) | (0x1f << 10), (sw_impedance[ca_term][i - 1] << 15) | (sw_impedance[ca_term][i] << 10)); - clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + clrsetbits32(&ch[0].ao.shu[0].drving[i], (0x1f << 5) | (0x1f << 0), (sw_impedance[ca_term][i - 1] << 5) | (sw_impedance[ca_term][i] << 0)); } - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17, + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17, sw_impedance[ca_term][0] << 17); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, + clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, sw_impedance[ca_term][1] << 22); SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[3], @@ -215,34 +215,34 @@ void dramc_sw_impedance_save_reg(u8 freq_group, SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); - clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); + clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); } static void transfer_pll_to_spm_control(void) { u8 shu_lev = (read32(&ch[0].ao.shustatus) >> 1) & 0x3; - clrsetbits_le32(&mtk_spm->poweron_config_set, + clrsetbits32(&mtk_spm->poweron_config_set, (0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0)); /* Set SPM pinmux */ - clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); - setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); - setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); + clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); + setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); + setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); - setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); - setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); + setbits32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); + setbits32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); shu_lev = (shu_lev == 1) ? 2 : 1; - clrsetbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28); - clrsetbits_le32(&mtk_spm->dramc_dpy_clk_sw_con2, + clrsetbits32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28); + clrsetbits32(&mtk_spm->dramc_dpy_clk_sw_con2, 0x3 << 2, shu_lev << 2); udelay(1); for (size_t chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { - clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31); - clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + clrbits32(&ch[chn].phy.pll1, 0x1 << 31); + clrbits32(&ch[chn].phy.pll2, 0x1 << 31); } } @@ -254,50 +254,50 @@ static void dramc_rx_input_delay_tracking(u8 chn) /* DVS mode to RG mode */ for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30); + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30); - clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9); - clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9); + clrsetbits32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9); + clrsetbits32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9); for (size_t r = 0; r < 2; r++) for (size_t b = 0; b < 2; b++) { - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29); - clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7], + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29); + clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[7], (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), (0x0 << 0) | (0x3f << 8) | (0x0 << 16) | (0x7f << 24)); - clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[1], + clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[1], (0xffff << 16) | (0xffff << 0), (0x2 << 16) | (0x2 << 0)); /* DQ/DQS Rx DLY adjustment for tracking mode */ - clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], + clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], (0x3 << 26) | (0x3 << 24) | (0x3 << 18) | (0x3 << 16)); } /* Rx DLY tracking setting (Static) */ - clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], + clrsetbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); - clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], + clrsetbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 29) | (0xf << 4) | (0x1 << 0), (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); for (u8 b = 0; b < 2; b++) { - clrsetbits_le32(&ch[chn].phy.b[b].dq[9], + clrsetbits32(&ch[chn].phy.b[b].dq[9], (0x7 << 28) | (0x7 << 24), (0x1 << 28) | (0x0 << 24)); - setbits_le32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); + setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31); } - clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); + clrbits32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); - setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); - setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); + setbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); + setbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); for (u8 rank = RANK_0; rank < RANK_MAX; rank++) for (u8 b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.r[rank].b[b].rxdvs[2], + clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2], (0x3 << 30) | (0x1 << 28) | (0x1 << 23), (0x2 << 30) | (0x1 << 28) | (0x1 << 23)); @@ -305,29 +305,29 @@ static void dramc_rx_input_delay_tracking(u8 chn) static void dramc_hw_dqs_gating_tracking(u8 chn) { - clrsetbits_le32(&ch[chn].ao.stbcal, + clrsetbits32(&ch[chn].ao.stbcal, (0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4), (0x3 << 26) | (0x1 << 0)); - clrsetbits_le32(&ch[chn].ao.stbcal1, + clrsetbits32(&ch[chn].ao.stbcal1, (0xffff << 16) | (0x1 << 8) | (0x1 << 6), (0x1 << 16) | (0x1 << 8) | (0x1 << 6)); - clrsetbits_le32(&ch[chn].phy.misc_ctrl0, + clrsetbits32(&ch[chn].phy.misc_ctrl0, (0x1 << 24) | (0x1f << 11) | (0xf << 0), (0x1 << 24) | (0x0 << 11) | (0x0 << 0)); - clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 31); - clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 31); - clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 31); + clrbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 31); + clrbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 31); + clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 31); } static void dramc_hw_gating_init(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrbits_le32(&ch[chn].ao.stbcal, + clrbits32(&ch[chn].ao.stbcal, (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); - setbits_le32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); - setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); + setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24); dramc_hw_dqs_gating_tracking(chn); } @@ -335,28 +335,28 @@ static void dramc_hw_gating_init(void) static void dramc_impedance_tracking_enable(void) { - setbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 10); + setbits32(&ch[0].phy.misc_ctrl0, 0x1 << 10); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) | + setbits32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) | (0x1 << 26) | (0x1 << 17) | (0x7 << 11)); - clrbits_le32(&ch[chn].ao.impcal, 0x1 << 30); - setbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 18); - setbits_le32(&ch[chn].ao.impcal, 0x1 << 19); + clrbits32(&ch[chn].ao.impcal, 0x1 << 30); + setbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 18); + setbits32(&ch[chn].ao.impcal, 0x1 << 19); } - setbits_le32(&ch[0].ao.impcal, 0x1 << 14); + setbits32(&ch[0].ao.impcal, 0x1 << 14); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); + setbits32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3)); } static void dramc_phy_low_power_enable(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { for (size_t b = 0; b < 2; b++) { - clrbits_le32(&ch[chn].phy.b[b].dll_fine_tune[2], + clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2], 0x3fffff << 10); write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800); } - clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], + clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x3fffff << 10, 0x2 << 10); } write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000); @@ -365,67 +365,67 @@ static void dramc_phy_low_power_enable(void) static void dramc_dummy_read_for_tracking_enable(u8 chn) { - setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16); + setbits32(&ch[chn].ao.dummy_rd, 0x3 << 16); for (size_t r = 0; r < 2; r++) for (size_t i = 0; i < 4; i++) write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i], 0xaaaa5555); - clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); + clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); for (size_t r = 0; r < 2; r++) { - clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr, + clrsetbits32(&ch[chn].ao.rk[r].dummy_rd_adr, (0x1ffff << 0) | (0x7ff << 17) | (0xf << 28), (0xffff << 0) | (0x3f0 << 17)); - clrbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); + clrbits32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0); } - clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); + clrbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20); } static void dramc_set_CKE_2_rank_independent(u8 chn) { - clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2); - clrsetbits_le32(&ch[chn].ao.ckectrl, + clrsetbits32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2); + clrsetbits32(&ch[chn].ao.ckectrl, (0x1 << 1) | (0xf << 8) | (0x7 << 13), (0x4 << 8) | (0x2 << 13)); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits_le32(&ch[chn].ao.shu[shu].conf[2], + setbits32(&ch[chn].ao.shu[shu].conf[2], (0x1 << 29) | (0x1 << 31)); - clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9); + clrbits32(&ch[chn].ao.dramctrl, 0x1 << 9); } static void dramc_pa_improve(u8 chn) { - clrbits_le32(&ch[chn].ao.clkar, 0xffff); - clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12); - clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); - clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); - clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19); - clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + clrbits32(&ch[chn].ao.clkar, 0xffff); + clrbits32(&ch[chn].ao.srefctrl, 0xf << 12); + clrbits32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); + clrbits32(&ch[chn].ao.zqcs, 0x1 << 19); + clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2); + clrbits32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2); } static void dramc_enable_dramc_dcm(void) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, (0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), (0x7 << 0) | (0x1 << 30) | (0x1 << 31)); - setbits_le32(&ch[chn].ao.clkar, 0x1 << 31); + setbits32(&ch[chn].ao.clkar, 0x1 << 31); } } void dramc_runtime_config(void) { - clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29); - clrbits_le32(&ch[1].ao.refctrl0, 0x1 << 29); + clrbits32(&ch[0].ao.refctrl0, 0x1 << 29); + clrbits32(&ch[1].ao.refctrl0, 0x1 << 29); transfer_pll_to_spm_control(); - setbits_le32(&mtk_spm->spm_power_on_val0, 0x1 << 25); + setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25); /* RX_TRACKING: ON */ for (u8 chn = 0; chn < CHANNEL_MAX; chn++) @@ -438,7 +438,7 @@ void dramc_runtime_config(void) /* HW_GATING DBG: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - clrbits_le32(&ch[chn].ao.stbcal2, + clrbits32(&ch[chn].ao.stbcal2, (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); /* DUMMY_READ_FOR_TRACKING: ON */ @@ -446,8 +446,8 @@ void dramc_runtime_config(void) dramc_dummy_read_for_tracking_enable(chn); /* ZQCS_ENABLE_LP4: ON */ - clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[1].ao.spcmdctrl, 0x1 << 30); /* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */ dramc_phy_low_power_enable(); @@ -456,7 +456,7 @@ void dramc_runtime_config(void) /* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry, + clrbits32(&ch[chn].ao.shu[shu].dqsg_retry, (0x1 << 1) | (0x3 << 13)); /* SPM_CONTROL_AFTERK: ON */ @@ -470,33 +470,33 @@ void dramc_runtime_config(void) for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { /* TEMP_SENSOR: ON */ - clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28); - setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); + clrbits32(&ch[chn].ao.spcmdctrl, 0x3 << 28); + setbits32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); /* PER_BANK_REFRESH: ON */ - clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); + clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); /* HW_SAVE_FOR_SR: ON */ - clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28)); - setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0); - clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22); + clrbits32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28)); + setbits32(&ch[chn].ao.refctrl1, 0x1 << 0); + clrsetbits32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22); /* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */ dramc_set_CKE_2_rank_independent(chn); /* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */ - clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2)); - clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19); + clrbits32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2)); + clrbits32(&ch[chn].ao.clkar, 0x1 << 19); /* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */ dramc_pa_improve(chn); /* DRAM DRS DISABLE */ - clrsetbits_le32(&ch[chn].ao.drsctrl, + clrsetbits32(&ch[chn].ao.drsctrl, (0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6), (0x1 << 19) | (0x3 << 12) | (0x8 << 8) | (0x3 << 4) | (0x1 << 2) | (0x1 << 0)); - setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26); + setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26); } enable_emi_dcm(); diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 16f28785d3..cd9f328ae6 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -154,8 +154,8 @@ static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_t tmp_0p5t = sum - (tmp_2t << DQ_DIV_SHIFT); } - clrsetbits_le32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift); - clrsetbits_le32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift); + clrsetbits32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift); + clrsetbits32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift); } static void move_dramc_tx_dqs(u8 chn, u8 byte, s8 shift_coarse_tune) @@ -279,36 +279,36 @@ static void dramc_write_dbi_onoff(bool onoff) static void dramc_phy_dcm_2_channel(u8 chn, bool en) { - clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8), + clrsetbits32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8), ((en ? 0 : 0x1) << 19) | ((en ? 0 : 0x1ff) << 9) | (1 << 8)); for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&shu->b[b].dq[8], 0x1fff << 19, + clrsetbits32(&shu->b[b].dq[8], 0x1fff << 19, ((en ? 0 : 0x7ff) << 22) | (0x1 << 21) | ((en ? 0 : 0x3) << 19)); - clrbits_le32(&shu->ca_cmd[8], 0x1fff << 19); + clrbits32(&shu->ca_cmd[8], 0x1fff << 19); } - clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20), + clrsetbits32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20), ((en ? 0x7 : 0) << 16) | ((en ? 0x7 : 0) << 20)); } void dramc_enable_phy_dcm(bool en) { for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) { - clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); - clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); - clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); + clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - setbits_le32(&shu->b[0].dll[0], 0x1); - setbits_le32(&shu->b[1].dll[0], 0x1); - setbits_le32(&shu->ca_dll[0], 0x1); + setbits32(&shu->b[0].dll[0], 0x1); + setbits32(&shu->b[1].dll[0], 0x1); + setbits32(&shu->ca_dll[0], 0x1); } - clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + clrsetbits32(&ch[chn].ao.dramc_pd_ctrl, (0x1 << 0) | (0x1 << 1) | (0x1 << 2) | (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) | @@ -324,16 +324,16 @@ void dramc_enable_phy_dcm(bool en) write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033e | (0x40 << (en ? 0x1 : 0))); - clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, + clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, (en ? 0 : 0x3) << 26); for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { u32 mask = 0x7 << 17; u32 value = (en ? 0x7 : 0) << 17; struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - clrsetbits_le32(&shu->b[0].dq[7], mask, value); - clrsetbits_le32(&shu->b[1].dq[7], mask, value); - clrsetbits_le32(&shu->ca_cmd[7], mask, value); + clrsetbits32(&shu->b[0].dq[7], mask, value); + clrsetbits32(&shu->b[1].dq[7], mask, value); + clrsetbits32(&shu->ca_cmd[7], mask, value); } dramc_phy_dcm_2_channel(chn, en); @@ -346,31 +346,31 @@ static void dramc_reset_delay_chain_before_calibration(void) for (size_t rank = 0; rank < RANK_MAX; rank++) { struct dramc_ddrphy_regs_shu_rk *rk; rk = &ch[chn].phy.shu[0].rk[rank]; - clrbits_le32(&rk->ca_cmd[0], 0xffffff << 0); - clrbits_le32(&rk->b[0].dq[0], 0xfffffff << 0); - clrbits_le32(&rk->b[1].dq[0], 0xfffffff << 0); - clrbits_le32(&rk->b[0].dq[1], 0xf << 0); - clrbits_le32(&rk->b[1].dq[1], 0xf << 0); + clrbits32(&rk->ca_cmd[0], 0xffffff << 0); + clrbits32(&rk->b[0].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[1].dq[0], 0xfffffff << 0); + clrbits32(&rk->b[0].dq[1], 0xf << 0); + clrbits32(&rk->b[1].dq[1], 0xf << 0); } } void dramc_hw_gating_onoff(u8 chn, bool on) { - clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14, + clrsetbits32(&ch[chn].ao.shuctrl2, 0x3 << 14, (on ? 0x3 : 0) << 14); - clrsetbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28); - clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24); - clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); + clrsetbits32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28); + clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24); + clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22); } static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) { struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0]; - clrsetbits_le32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); - clrsetbits_le32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); - clrbits_le32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); - clrbits_le32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); + clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20); + clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20); + clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13)); + clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13)); } void dramc_apply_config_before_calibration(u8 freq_group) @@ -378,55 +378,55 @@ void dramc_apply_config_before_calibration(u8 freq_group) dramc_enable_phy_dcm(false); dramc_reset_delay_chain_before_calibration(); - setbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16); - setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24); - clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); + setbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16); + setbits32(&ch[0].ao.spcmdctrl, 0x1 << 24); + clrsetbits32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); + setbits32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); - clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18); - clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 31); - clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); - clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 26); - clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 25); + clrbits32(&ch[0].ao.dramctrl, 0x1 << 18); + clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 31); + clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30); + clrbits32(&ch[0].ao.dqsoscr, 0x1 << 26); + clrbits32(&ch[0].ao.dqsoscr, 0x1 << 25); dramc_write_dbi_onoff(false); dramc_read_dbi_onoff(false); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29); - setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24); + setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 29); + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 24); for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); + setbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); - clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); + clrbits32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); dramc_hw_gating_onoff(chn, false); - clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28); + clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28); - setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); - clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); - clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24); - setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17); - clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); - clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); - clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11)); + clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18); + clrbits32(&ch[chn].ao.mrs, 0x3 << 24); + setbits32(&ch[chn].ao.mpc_option, 0x1 << 17); + clrsetbits32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); dramc_rx_input_delay_tracking_init_by_freq(chn); - setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25); - setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0); + setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25); + setbits32(&ch[chn].ao.drsctrl, 0x1 << 0); if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) - clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); else - setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); } for (size_t r = 0; r < 2; r++) { for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2], (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); - clrbits_le32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); } } @@ -437,51 +437,51 @@ static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr) mr->MR13Value & ~(0x1 << 3)); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); + clrbits32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19); } void dramc_apply_config_after_calibration(const struct mr_value *mr) { for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000); - clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7); - clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2); - clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); + clrbits32(&ch[chn].ao.refctrl1, 0x1 << 7); + clrbits32(&ch[chn].ao.shuctrl, 0x1 << 2); + clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 6); dramc_set_mr13_vrcg_to_Normal(chn, mr); - clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x3); - clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x3); - clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x3); - setbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 5); - setbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 5); - setbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 5); + clrbits32(&ch[chn].phy.b[0].dq[6], 0x3); + clrbits32(&ch[chn].phy.b[1].dq[6], 0x3); + clrbits32(&ch[chn].phy.ca_cmd[6], 0x3); + setbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 5); + setbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 5); + setbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 5); - clrbits_le32(&ch[chn].ao.impcal, 0x3 << 24); - clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x4); - clrbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0xf); + clrbits32(&ch[chn].ao.impcal, 0x3 << 24); + clrbits32(&ch[chn].phy.misc_imp_ctrl0, 0x4); + clrbits32(&ch[chn].phy.misc_cg_ctrl0, 0xf); - clrbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 31); - clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 25); + clrbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 31); + clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 25); - setbits_le32(&ch[chn].ao.spcmdctrl, 1 << 29); - setbits_le32(&ch[chn].ao.dqsoscr, 1 << 24); + setbits32(&ch[chn].ao.spcmdctrl, 1 << 29); + setbits32(&ch[chn].ao.dqsoscr, 1 << 24); for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) - clrbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); + clrbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); - clrbits_le32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7)); + clrbits32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7)); dramc_cke_fix_onoff(chn, false, false); - clrbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); + clrbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26); - clrbits_le32(&ch[chn].ao.eyescan, 0x7 << 8); - clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); + clrbits32(&ch[chn].ao.eyescan, 0x7 << 8); + clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28); } } static void dramc_rx_dqs_isi_pulse_cg_switch(u8 chn, bool flag) { for (size_t b = 0; b < 2; b++) - clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 1 << 5, + clrsetbits32(&ch[chn].phy.b[b].dq[6], 1 << 5, (flag ? 1 : 0) << 5); } @@ -600,7 +600,7 @@ static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) static void dramc_engine2_end(u8 chn, u32 dummy_rd) { - clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17); + clrbits32(&ch[chn].ao.test2_4, 0x1 << 17); write32(&ch[chn].ao.dummy_rd, dummy_rd); } @@ -717,12 +717,12 @@ static void dram_phy_reset(u8 chn) { SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 1); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1); - clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); - clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); + clrbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); + clrbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); udelay(1); - setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); - setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); + setbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); + setbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0); SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 0); } @@ -737,18 +737,18 @@ static void dramc_set_gating_mode(u8 chn, bool mode) } for (size_t b = 0; b < 2; b++) { - clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14); - setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5); + clrsetbits32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14); + setbits32(&ch[chn].phy.b[b].dq[9], 0x1 << 5); } - clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); - setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30); + clrsetbits32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); + setbits32(&ch[chn].ao.stbcal, 0x1 << 30); - clrbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); - clrbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); + clrbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); udelay(1); - setbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); - setbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0)); } static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) @@ -773,7 +773,7 @@ static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank) static void set_selph_gating_value(uint32_t *addr, u8 dly, u8 dly_p1) { - clrsetbits_le32(addr, 0x77777777, + clrsetbits32(addr, 0x77777777, (dly << 0) | (dly << 8) | (dly << 16) | (dly << 24) | (dly_p1 << 4) | (dly_p1 << 12) | (dly_p1 << 20) | (dly_p1 << 28)); } @@ -788,11 +788,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank, dramc_rx_dqs_isi_pulse_cg_switch(chn, true); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, 0x77777777, (best_coarse_tune2t[0] << 0) | (best_coarse_tune2t[1] << 8) | (best_coarse_tune2t_p1[0] << 4) | (best_coarse_tune2t_p1[1] << 12)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, 0x77777777, (best_coarse_tune0p5t[0] << 0) | (best_coarse_tune0p5t[1] << 8) | (best_coarse_tune0p5t_p1[0] << 4) | (best_coarse_tune0p5t_p1[1] << 12)); @@ -827,11 +827,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank, } } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, 0x77777777, (best_coarse_rodt[0] << 0) | (best_coarse_rodt[1] << 8) | (best_coarse_rodt_p1[0] << 4) | (best_coarse_rodt_p1[1] << 12)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, 0x77777777, (best_coarse_0p5t_rodt[0] << 0) | (best_coarse_0p5t_rodt[1] << 8) | (best_coarse_0p5t_rodt_p1[0] << 4) | (best_coarse_0p5t_rodt_p1[1] << 12)); @@ -1063,7 +1063,7 @@ static void dramc_rx_rd_dqc_init(u8 chn, u8 rank) u16 temp_value = 0; for (size_t b = 0; b < 2; b++) - clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7); + clrbits32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7); SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank); SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1); @@ -1213,17 +1213,17 @@ static void dramc_set_tx_dly_factor(u8 chn, u8 rk, if (*dq_small_reg != dly_tune.coarse_tune_small) { if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) { - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0], 0x77777777, dly_large | (dly_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2], 0x77777777, dly_small | (dly_small_oen << 16)); } if (type == TX_WIN_DQ_DQM) { /* Large coarse_tune setting */ - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1], 0x77777777, dly_large | (dly_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3], + clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3], 0x77777777, dly_small | (dly_small_oen << 16)); } } @@ -1480,13 +1480,13 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type, } for (size_t rank = rank_start; rank < RANK_MAX; rank++) { - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], 0x77777777, dq_large | (dq_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], 0x77777777, dq_small | (dq_small_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], 0x77777777, dqm_large | (dqm_large_oen << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], 0x77777777, dqm_small | (dqm_small_oen << 16)); for (size_t byte = 0; byte < 2; byte++) @@ -1503,15 +1503,15 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type, if (type != TX_WIN_DQ_ONLY) continue; - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f, (dqdly_tune[0].fine_tune << 8) | (dqdly_tune[1].fine_tune << 0) | (dqmdly_tune[0].fine_tune << 24) | (dqmdly_tune[1].fine_tune << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16), + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16), (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16), + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16), (dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16)); - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16), + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16), (dqmdly_tune[0].fine_tune << 0) | (dqmdly_tune[1].fine_tune << 16)); } } @@ -1525,7 +1525,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, for (u8 byte = 0; byte < DQS_NUMBER; byte++) { value = (dqsdly_byte[byte] << 24) | (dqsdly_byte[byte] << 16) | (dqmdly_byte[byte] << 8) | (dqmdly_byte[byte] << 0); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value); + clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value); } dram_phy_reset(chn); @@ -1538,7 +1538,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank, (dly[index + 1].best_dqdly << 16) | (dly[index].best_dqdly << 8) | (dly[index].best_dqdly << 0); - clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num], + clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num], 0x3f3f3f3f, value); } } @@ -1817,11 +1817,11 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) { for (size_t byte = 0; byte < 2; byte++) { write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], 0); - clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1], + clrbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1], 0xf); } - setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); - setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 7); + setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7); + setbits32(&ch[chn].ao.dqsoscr, 0x1 << 7); if (fsp == FSP_1) vref_step = 2; } @@ -2070,7 +2070,7 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) dqs, best_coarse_tune2t_p1[rank][dqs]); } - clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, 0x77777777, (best_coarse_tune2t[rank][0] << 0) | (best_coarse_tune2t[rank][1] << 8) | @@ -2085,13 +2085,13 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group) SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[0].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl); SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[1].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl); - clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + clrsetbits32(&ch[chn].ao.shu[0].rankctl, (0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf, (read_dqsinctl << 28) | (rankinctl_root << 20) | (rankinctl_root << 24) | rankinctl_root); u8 ROEN = read32(&ch[chn].ao.shu[0].odtctrl) & 0x1; - clrsetbits_le32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1), + clrsetbits32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1), (0xff << 8) | (0x9 << 2) | ROEN); } diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 604592f5cb..7f5ac0a747 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -49,19 +49,19 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) txdiv1 = 0; } - clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); - setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); udelay(30); - clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); pcw <<= 24; pcw /= CLK26M_HZ / MHz; write32(&mipi_tx->pll_con0, pcw); - clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); udelay(30); - setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); /* BG_LPF_EN / BG_CORE_EN */ write32(&mipi_tx->lane_con, 0x3fff0180); @@ -69,13 +69,13 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) write32(&mipi_tx->lane_con, 0x3fff00c0); /* Switch OFF each Lane */ - clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); - setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); + setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); } void mtk_dsi_reset(void) diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 7cd631ca0b..cf104f8485 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -157,7 +157,7 @@ size_t sdram_size(void) static void set_rank_info_to_conf(const struct sdram_params *params) { bool is_dual_rank = (params->emi_cona_val & (0x1 << 17)) != 0; - clrsetbits_le32(&ch[0].ao.rstmask, 0x1 << 12, + clrsetbits32(&ch[0].ao.rstmask, 0x1 << 12, (is_dual_rank ? 0 : 1) << 12); } @@ -297,8 +297,8 @@ static void emi_init2(const struct sdram_params *params) { emi_esl_setting2(); - setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); - setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); + setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); + setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0); @@ -311,14 +311,14 @@ static void emi_init2(const struct sdram_params *params) static void dramc_init_pre_settings(void) { - clrsetbits_le32(&ch[0].phy.ca_cmd[8], + clrsetbits32(&ch[0].phy.ca_cmd[8], (0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) | (0x1f << 8) | (0x1f << 0), (0x1 << 19) | (0xa << 8) | (0xa << 0)); - setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 12); - clrbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 13); - setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 31); + setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 12); + clrbits32(&ch[0].phy.misc_ctrl1, 0x1 << 13); + setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31); } static void dramc_ac_timing_optimize(u8 freq_group) @@ -331,20 +331,20 @@ static void dramc_ac_timing_optimize(u8 freq_group) }; for (size_t chn = 0; chn < CHANNEL_MAX; chn++) { - clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + clrsetbits32(&ch[chn].ao.shu[0].actim[3], 0xff << 16, rf_cab_opt[freq_group].rfc << 16); - clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, + clrbits32(&ch[chn].ao.shu[0].ac_time_05t, rf_cab_opt[freq_group].rfc_05t << 2); - clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], + clrsetbits32(&ch[chn].ao.shu[0].actim[4], 0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0); } } static void spm_pinmux_setting(void) { - clrsetbits_le32(&mtk_spm->poweron_config_set, + clrsetbits32(&mtk_spm->poweron_config_set, (0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0)); - clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); + clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); write32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); } @@ -377,11 +377,11 @@ static void init_dram(const struct sdram_params *params, u8 freq_group, void enable_emi_dcm(void) { - clrbits_le32(&emi_regs->conm, 0xff << 24); - clrbits_le32(&emi_regs->conn, 0xff << 24); + clrbits32(&emi_regs->conm, 0xff << 24); + clrbits32(&emi_regs->conn, 0xff << 24); for (size_t chn = 0; chn < CHANNEL_MAX; chn++) - clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24); + clrbits32(&ch[chn].emi.chn_conb, 0xff << 24); } struct shuffle_reg_addr { @@ -456,18 +456,18 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle) value = read32(src_addr) & 0x7f; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits_le32(dst_addr, 0x7f << 0x8, value << 0x8); + clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits_le32(dst_addr, 0x7f << 0x16, value << 0x16); + clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16); /* DRAMC-exception-2 */ src_addr = (u8 *)&ch[chn].ao.dvfsdll; value = (read32(src_addr) >> 1) & 0x1; if (dst_shuffle == DRAM_DFS_SHUFFLE_2) - clrsetbits_le32(src_addr, 0x1 << 2, value << 2); + clrsetbits32(src_addr, 0x1 << 2, value << 2); else if (dst_shuffle == DRAM_DFS_SHUFFLE_3) - clrsetbits_le32(src_addr, 0x1 << 3, value << 3); + clrsetbits32(src_addr, 0x1 << 3, value << 3); /* PHY */ for (index = 0; index < ARRAY_SIZE(phy_regs); index++) { diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c index 3eccfbd50d..0664678dd9 100644 --- a/src/soc/mediatek/mt8183/gpio.c +++ b/src/soc/mediatek/mt8183/gpio.c @@ -34,15 +34,15 @@ static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, if (enable == GPIO_PULL_ENABLE) { if (select == GPIO_PULL_DOWN) - setbits_le32(reg, 1 << (bit + 2)); + setbits32(reg, 1 << (bit + 2)); else - clrbits_le32(reg, 1 << (bit + 2)); + clrbits32(reg, 1 << (bit + 2)); } if (enable == GPIO_PULL_ENABLE) - clrsetbits_le32(reg, 3 << bit, 1 << bit); + clrsetbits32(reg, 3 << bit, 1 << bit); else - clrbits_le32(reg, 3 << bit); + clrbits32(reg, 3 << bit); } static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable, @@ -53,15 +53,15 @@ static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable, if (enable == GPIO_PULL_ENABLE) { if (select == GPIO_PULL_DOWN) - clrbits_le32(reg + SEL_OFFSET, 1 << bit); + clrbits32(reg + SEL_OFFSET, 1 << bit); else - setbits_le32(reg + SEL_OFFSET, 1 << bit); + setbits32(reg + SEL_OFFSET, 1 << bit); } if (enable == GPIO_PULL_ENABLE) - setbits_le32(reg + EN_OFFSET, 1 << bit); + setbits32(reg + EN_OFFSET, 1 << bit); else - clrbits_le32(reg + EN_OFFSET, 1 << bit); + clrbits32(reg + EN_OFFSET, 1 << bit); } void gpio_set_pull(gpio_t gpio, enum pull_enable enable, @@ -112,23 +112,23 @@ enum { void gpio_set_i2c_eh_rsel(void) { - clrsetbits_le32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL0) | I2C_EH_RSL_MASK(SDA0) | I2C_EH_RSL_MASK(SCL1) | I2C_EH_RSL_MASK(SDA1), I2C_EH_RSL_VAL(SCL0) | I2C_EH_RSL_VAL(SDA0) | I2C_EH_RSL_VAL(SCL1) | I2C_EH_RSL_VAL(SDA1)); - clrsetbits_le32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL2) | I2C_EH_RSL_MASK(SDA2) | I2C_EH_RSL_MASK(SCL4) | I2C_EH_RSL_MASK(SDA4), I2C_EH_RSL_VAL(SCL2) | I2C_EH_RSL_VAL(SDA2) | I2C_EH_RSL_VAL(SCL4) | I2C_EH_RSL_VAL(SDA4)); - clrsetbits_le32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL3) | I2C_EH_RSL_MASK(SDA3), I2C_EH_RSL_VAL(SCL3) | I2C_EH_RSL_VAL(SDA3)); - clrsetbits_le32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET, + clrsetbits32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET, I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5), I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5)); } @@ -153,17 +153,17 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select, reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET); offset = 0; } else if (pad_select == SPI_PAD1_MASK) { - clrsetbits_le32((void *)IOCFG_RM_BASE + + clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET, 0xf | 0xf << 20, reg_val | reg_val << 20); - clrsetbits_le32((void *)IOCFG_RM_BASE + + clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV1_OFFSET, 0xf << 16, reg_val << 16); return; } break; case 2: - clrsetbits_le32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET, + clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET, 0xf << 8 | 0xf << 12, reg_val << 8 | reg_val << 12); return; @@ -181,5 +181,5 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select, break; } - clrsetbits_le32(reg, 0xf << offset, reg_val << offset); + clrsetbits32(reg, 0xf << offset, reg_val << offset); } diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c index aa97756db2..a1405dd0e7 100644 --- a/src/soc/mediatek/mt8183/md_ctrl.c +++ b/src/soc/mediatek/mt8183/md_ctrl.c @@ -24,10 +24,10 @@ static void internal_md_power_down(void) { /* Gating MD clock */ - setbits_le32(&mtk_topckgen->clk_mode, + setbits32(&mtk_topckgen->clk_mode, TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M); /* Release SRCCLKENA */ - clrbits_le32(&mt8183_infracfg->infra_misc2, + clrbits32(&mt8183_infracfg->infra_misc2, INFRA_MISC2_SRCCLKENA_RELEASE); } diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 5368077318..ff61303337 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -282,7 +282,7 @@ static const struct rate rates[] = { void pll_set_pcw_change(const struct pll *pll) { - setbits_le32(pll->div_reg, PLL_PCW_CHG); + setbits32(pll->div_reg, PLL_PCW_CHG); } void mt_pll_init(void) @@ -290,20 +290,20 @@ void mt_pll_init(void) int i; /* enable univpll & mainpll div */ - setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16); + setbits32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16); /* enable clock square1 low-pass filter */ - setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2); + setbits32(&mtk_apmixed->ap_pll_con0, 0x2); /* xPLL PWR ON */ for (i = 0; i < APMIXED_PLL_MAX; i++) - setbits_le32(plls[i].pwr_reg, PLL_PWR_ON); + setbits32(plls[i].pwr_reg, PLL_PWR_ON); udelay(PLL_PWR_ON_DELAY); /* xPLL ISO Disable */ for (i = 0; i < APMIXED_PLL_MAX; i++) - clrbits_le32(plls[i].pwr_reg, PLL_ISO); + clrbits32(plls[i].pwr_reg, PLL_ISO); udelay(PLL_ISO_DELAY); @@ -319,7 +319,7 @@ void mt_pll_init(void) /* xPLL Frequency Enable */ for (i = 0; i < APMIXED_PLL_MAX; i++) - setbits_le32(plls[i].reg, PLL_EN); + setbits32(plls[i].reg, PLL_EN); /* wait for PLL stable */ udelay(PLL_EN_DELAY); @@ -327,32 +327,32 @@ void mt_pll_init(void) /* xPLL DIV RSTB */ for (i = 0; i < APMIXED_PLL_MAX; i++) { if (plls[i].rstb_shift != NO_RSTB_SHIFT) - setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift); + setbits32(plls[i].reg, 1 << plls[i].rstb_shift); } /* MCUCFG CLKMUX */ - clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1); - clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1); - clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2); + clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1); + clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1); + clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2); - clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, + clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK, MUX_SRC_ARMPLL); - clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK, + clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK, MUX_SRC_ARMPLL); - clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK, + clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK, MUX_SRC_ARMPLL); /* enable infrasys DCM */ - setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); - clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, + setbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + clrsetbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON); - setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); - clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); - clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl, + setbits32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON); + clrbits32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK); + clrsetbits32(&mt8183_infracfg->peri_bus_dcm_ctrl, DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON); /* enable [11] for change i2c module source clock to TOPCKGEN */ - setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); + setbits32(&mt8183_infracfg->module_clk_sel, 0x1 << 11); /* * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS! @@ -361,19 +361,19 @@ void mt_pll_init(void) mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel); /* enable [14] dramc_pll104m_ck */ - setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); /* enable audio clock */ - setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); + setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); /* enable intbus clock */ - setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); + setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); /* enable infra clock */ - setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); + setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); /* enable mtkaif 26m clock */ - setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); + setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } void mt_pll_raise_ca53_freq(u32 freq) diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index 7672db7993..c77d7ef7d3 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -127,10 +127,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | - SPI_CFG1_CS_IDLE_MASK, - (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | - ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); + clrsetbits32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | + SPI_CFG1_CS_IDLE_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); } const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 9a08782953..024fe1c9fc 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -77,16 +77,16 @@ static int spm_register_init(void) MD_DDR_EN_1_DBC_LEN | CONN_DDR_EN_DBC_LEN); - clrsetbits_le32(&mtk_spm->spare_ack_mask, - SPARE_ACK_MASK_B_BIT1, - SPARE_ACK_MASK_B_BIT0); + clrsetbits32(&mtk_spm->spare_ack_mask, + SPARE_ACK_MASK_B_BIT1, + SPARE_ACK_MASK_B_BIT0); write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN); write32(&mtk_spm->spm_pc_trace_con, SPM_PC_TRACE_OFFSET | SPM_PC_TRACE_HW_EN_LSB); - setbits_le32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); + setbits32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); return 0; } @@ -131,9 +131,9 @@ static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) write32(&mtk_spm->pcm_pwr_io_en, 0); - clrsetbits_le32(&mtk_spm->pcm_con1, - PCM_TIMER_EN_LSB, - SPM_REGWR_CFG_KEY); + clrsetbits32(&mtk_spm->pcm_con1, + PCM_TIMER_EN_LSB, + SPM_REGWR_CFG_KEY); write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index 559034eacb..857d3dc56d 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -16,7 +16,7 @@ #include <arch/barrier.h> #include <cbfs.h> #include <console/console.h> -#include <arch/mmio.h> +#include <device/mmio.h> #include <soc/sspm.h> #include <string.h> diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 55d80ed567..2b450c5672 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -149,7 +149,7 @@ void usb_setup_utmip(void *usb_base) int khz = clock_get_pll_input_khz(); /* Stop UTMI+ crystal clock while we mess with its settings */ - clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + clrbits32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ @@ -203,7 +203,7 @@ void usb_setup_utmip(void *usb_base) 25 * khz / 10 << 0); /* TODO: what's this, really? */ udelay(1); - setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + setbits32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ write32(&usb->suspend_ctrl, 1 << 12 | /* UTMI+ enable */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index bb0343d432..46ac4aca5d 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -203,13 +203,13 @@ void sor_clock_stop(void) * FIXME: this has to be cleaned up a bit more. * Waiting on some new info from Nvidia. */ - clrbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1); + clrbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0 | SOR0_CLK_SEL1); } void sor_clock_start(void) { /* uses PLLP, has a non-standard bit layout. */ - setbits_le32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0); + setbits32(&clk_rst->clk_src_sor, SOR0_CLK_SEL0); } static void init_pll(u32 *base, u32 *misc, const union pll_fields pll, u32 lock) @@ -240,7 +240,7 @@ static void init_utmip_pll(void) int khz = clock_get_pll_input_khz(); /* Shut off PLL crystal clock while we mess with it */ - clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ + clrbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ udelay(1); write32(&clk_rst->utmip_pll_cfg0, /* 960MHz * 1 / 80 == 12 MHz */ @@ -263,7 +263,7 @@ static void init_utmip_pll(void) 0 << 2 | /* SAMP_B/XHOST pwrdn */ 0 << 0); /* SAMP_A/USBD pwrdn */ - setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ + setbits32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ } /* Graphics just has to be different. There's a few more bits we @@ -401,9 +401,9 @@ void clock_early_uart(void) { write32(&clk_rst->clk_src_uarta, CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900)); - setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); + setbits32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); - clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); + clrbits32(&clk_rst->rst_dev_l, CLK_L_UARTA); } /* Enable output clock (CLK1~3) for external peripherals. */ @@ -411,13 +411,13 @@ void clock_external_output(int clk_id) { switch (clk_id) { case 1: - setbits_le32(&pmc->clk_out_cntrl, 1 << 2); + setbits32(&pmc->clk_out_cntrl, 1 << 2); break; case 2: - setbits_le32(&pmc->clk_out_cntrl, 1 << 10); + setbits32(&pmc->clk_out_cntrl, 1 << 10); break; case 3: - setbits_le32(&pmc->clk_out_cntrl, 1 << 18); + setbits32(&pmc->clk_out_cntrl, 1 << 18); break; default: printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n", @@ -461,7 +461,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, (p << PLL_BASE_DIVP_SHIFT)); write32(&clk_rst->pllm_base, base); - setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE); + setbits32(&clk_rst->pllm_base, PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); @@ -475,7 +475,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, udelay(10); /* Put OUT1 out of reset state (start to output). */ - setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); + setbits32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE); /* Enable and start MEM(MC) and EMC. */ clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0); @@ -492,7 +492,7 @@ void clock_cpu0_config(void *entry) write32(evp_cpu_reset, (uintptr_t)&maincpu_setup); /* Set active CPU cluster to G */ - clrbits_le32(&flow->cluster_control, 1); + clrbits32(&flow->cluster_control, 1); // Set up cclk_brst and divider. write32(&clk_rst->cclk_brst_pol, @@ -511,9 +511,9 @@ void clock_cpu0_config(void *entry) write32(&clk_rst->clk_cpu_cmplx_clr, cpu_cmplx_clr); // Enable other CPU related clocks. - setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); + setbits32(&clk_rst->clk_out_enb_l, CLK_L_CPU); + setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + setbits32(&clk_rst->clk_out_enb_v, CLK_V_CPULP); } void clock_cpu0_remove_reset(void) @@ -573,7 +573,7 @@ void clock_init(void) SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* Change the oscillator drive strength (from U-Boot -- why?) */ - clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, + clrsetbits32(&clk_rst->osc_ctrl, OSC_XOFS_MASK, OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); /* @@ -581,11 +581,11 @@ void clock_init(void) * "should update same value in PMC_OSC_EDPD_OVER XOFS * field for warmboot " */ - clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, + clrsetbits32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ - clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); + clrbits32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32(&clk_rst->pllp_outa, diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 761bb6bce5..78a8d10e00 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -82,7 +82,7 @@ struct apb_dma_channel * const dma_claim(void) * Set global enable bit, otherwise register access to channel * DMA registers will not be possible. */ - setbits_le32(&apb_dma->command, APB_COMMAND_GEN); + setbits32(&apb_dma->command, APB_COMMAND_GEN); for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { regs = apb_dma_channels[i].regs; @@ -122,7 +122,7 @@ void dma_release(struct apb_dma_channel * const channel) return; } - clrbits_le32(&apb_dma->command, APB_COMMAND_GEN); + clrbits32(&apb_dma->command, APB_COMMAND_GEN); } int dma_start(struct apb_dma_channel * const channel) @@ -130,7 +130,7 @@ int dma_start(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Set ENB bit for this channel */ - setbits_le32(®s->csr, APB_CSR_ENB); + setbits32(®s->csr, APB_CSR_ENB); return 0; } @@ -140,7 +140,7 @@ int dma_stop(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Clear ENB bit for this channel */ - clrbits_le32(®s->csr, APB_CSR_ENB); + clrbits32(®s->csr, APB_CSR_ENB); return 0; } diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 00744ce596..f99e786180 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -231,8 +231,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div, printk(BIOS_ERR, "%s clock divisor overflow!", name); hlt(); } - clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - src << CLK_SOURCE_SHIFT | div); + clrsetbits32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + src << CLK_SOURCE_SHIFT | div); } #define clock_configure_irregular_source(device, src, freq, src_id) \ diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 9f3e355ca4..3f1ee7ee95 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -93,12 +93,12 @@ int power_reset_status(void) void ram_repair(void) { // Request RAM repair for cluster 0 - setbits_le32(&flow->ram_repair, RAM_REPAIR_REQ); + setbits32(&flow->ram_repair, RAM_REPAIR_REQ); // Poll for completion while (!(read32(&flow->ram_repair) & RAM_REPAIR_STS)) ; // Request RAM repair for cluster 1 - setbits_le32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); + setbits32(&flow->ram_repair_cluster1, RAM_REPAIR_REQ); // Poll for completion while (!(read32(&flow->ram_repair_cluster1) & RAM_REPAIR_STS)) ; diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 9af116c56b..cf529257a7 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -34,7 +34,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) { - clrsetbits_le32(addr, mask, (value & mask)); + clrsetbits32(addr, mask, (value & mask)); } /* PMC must be configured before clock-enable and de-reset of MC/EMC. */ @@ -77,17 +77,17 @@ static void sdram_start_clocks(const struct sdram_params *param) static void sdram_deassert_clock_enable_signal(const struct sdram_params *param, struct tegra_pmc_regs *regs) { - clrbits_le32(®s->por_dpd_ctrl, - PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK); + clrbits32(®s->por_dpd_ctrl, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK); udelay(param->PmcPorDpdCtrlWait); } static void sdram_deassert_sel_dpd(const struct sdram_params *param, struct tegra_pmc_regs *regs) { - clrbits_le32(®s->por_dpd_ctrl, - (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK | - PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK)); + clrbits32(®s->por_dpd_ctrl, + (PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK | + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK)); /* * Note NVIDIA recommended to always do 10us delay here and ignore * BCT.PmcPorDpdCtrlWait. @@ -439,8 +439,8 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, struct tegra_emc_regs *regs) { volatile uint32_t dummy = 0; - clrbits_le32(®s->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | - EMC_PIN_CKE_MASK)); + clrbits32(®s->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | + EMC_PIN_CKE_MASK)); /* * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. @@ -449,7 +449,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, udelay(200 + param->EmcPinExtraWait); /* Deassert reset */ - setbits_le32(®s->pin, EMC_PIN_RESET_INACTIVE); + setbits32(®s->pin, EMC_PIN_RESET_INACTIVE); /* * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. @@ -458,7 +458,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, udelay(500 + param->EmcPinExtraWait); /* Enable clock enable signal */ - setbits_le32(®s->pin, EMC_PIN_CKE_NORMAL); + setbits32(®s->pin, EMC_PIN_CKE_NORMAL); /* * Assert dummy read of PIN register to ensure above write to PIN * register went through. 200 is the recommended value by NVIDIA. @@ -547,8 +547,8 @@ static void sdram_enable_arbiter(const struct sdram_params *param) { /* TODO(hungte) Move values here to standalone header file. */ uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0); - setbits_le32(AHB_ARBITRATION_XBAR_CTRL, - param->AhbArbitrationXbarCtrlMemInitDone << 16); + setbits32(AHB_ARBITRATION_XBAR_CTRL, + param->AhbArbitrationXbarCtrlMemInitDone << 16); } static void sdram_lock_carveouts(const struct sdram_params *param, diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 27ae1faf22..007d189bc9 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -184,13 +184,13 @@ struct tegra_spi_channel *tegra_spi_init(unsigned int bus) return NULL; /* software drives chip-select, set value to high */ - setbits_le32(&spi->regs->command1, + setbits32(&spi->regs->command1, SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); /* 8-bit transfers, unpacked mode, most significant bit first */ - clrbits_le32(&spi->regs->command1, + clrbits32(&spi->regs->command1, SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); - setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); return spi; } @@ -265,7 +265,7 @@ static void dump_fifo_status(struct tegra_spi_channel *spi) static void clear_fifo_status(struct tegra_spi_channel *spi) { - clrbits_le32(&spi->regs->fifo_status, + clrbits32(&spi->regs->fifo_status, SPI_FIFO_STATUS_ERR | SPI_FIFO_STATUS_TX_FIFO_OVF | SPI_FIFO_STATUS_TX_FIFO_UNR | @@ -372,11 +372,11 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, enable_mask = SPI_CMD1_RX_EN; } - setbits_le32(&spi->regs->fifo_status, flush_mask); + setbits32(&spi->regs->fifo_status, flush_mask); while (read32(&spi->regs->fifo_status) & flush_mask) ; - setbits_le32(&spi->regs->command1, enable_mask); + setbits32(&spi->regs->command1, enable_mask); /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and * PIO transfers */ @@ -396,8 +396,8 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, static void tegra_spi_pio_start(struct tegra_spi_channel *spi) { - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->command1, SPI_CMD1_GO); /* Make sure the write to command1 completes. */ read32(&spi->regs->command1); } @@ -414,7 +414,7 @@ static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) u8 *p = spi->in_buf; struct stopwatch sw; - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); /* * Allow some time in case the Rx FIFO does not yet have @@ -446,19 +446,19 @@ static void setup_dma_params(struct tegra_spi_channel *spi, struct apb_dma_channel *dma) { /* APB bus width = 8-bits, address wrap for each word */ - clrbits_le32(&dma->regs->apb_seq, + clrbits32(&dma->regs->apb_seq, APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), * no address wrapping */ - clrsetbits_le32(&dma->regs->ahb_seq, + clrsetbits32(&dma->regs->ahb_seq, (AHB_BURST_MASK << AHB_BURST_SHIFT), 4 << AHB_BURST_SHIFT); /* Set ONCE mode to transfer one "block" at a time (64KB) and enable * flow control. */ - clrbits_le32(&dma->regs->csr, + clrbits32(&dma->regs->csr, APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT); - setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | + setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | (spi->req_sel << APB_CSR_REQ_SEL_SHIFT)); } @@ -493,7 +493,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_out->regs->apb_ptr, (u32)&spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (u32)spi->out_buf); - setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); + setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); write32(&spi->dma_out->regs->wcount, wcount); } else { @@ -506,7 +506,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_in->regs->apb_ptr, (u32)&spi->regs->rx_fifo); write32(&spi->dma_in->regs->ahb_ptr, (u32)spi->in_buf); - clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); + clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); write32(&spi->dma_in->regs->wcount, wcount); } @@ -523,12 +523,12 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) * (set bit to clear) between each transaction. Otherwise the next * transaction does not start. */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); if (spi->dma_out) - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_TX_EN); if (spi->dma_in) - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_RX_EN); /* * To avoid underrun conditions, enable APB DMA before SPI DMA for @@ -536,7 +536,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ if (spi->dma_out) dma_start(spi->dma_out); - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); @@ -555,7 +555,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_in)) ; /* this shouldn't take long, no udelay */ dma_stop(spi->dma_in); - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN); dma_release(spi->dma_in); } @@ -566,7 +566,7 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_out)) { spi_delay(spi, todo - spi_byte_count(spi)); } - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN); dma_stop(spi->dma_out); dma_release(spi->dma_out); } diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c index 716c900fec..60ca16ca4e 100644 --- a/src/soc/nvidia/tegra210/addressmap.c +++ b/src/soc/nvidia/tegra210/addressmap.c @@ -297,14 +297,14 @@ void gpu_region_init(void) write32(&mc->security_carveout2_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout2_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout2_cfg0, MC_SECURITY_CARVEOUT_LOCKED); /* Set the carveout3 base to 0, unused */ write32(&mc->security_carveout3_bom, 0); write32(&mc->security_carveout3_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout3_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout3_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } void nvdec_region_init(void) @@ -322,7 +322,7 @@ void nvdec_region_init(void) write32(&mc->security_carveout1_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout1_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout1_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } void tsec_region_init(void) @@ -345,8 +345,8 @@ void tsec_region_init(void) write32(&mc->security_carveout5_bom_hi, 0); /* Set the locked bit. This will lock out any other writes! */ - setbits_le32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED); - setbits_le32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED); + setbits32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED); } void vpr_region_init(void) diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 55ee50bcdb..9117654e2a 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -255,13 +255,13 @@ void sor_clock_stop(void) * FIXME: this has to be cleaned up a bit more. * Waiting on some new info from Nvidia. */ - clrbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0 | SOR0_CLK_SEL1); + clrbits32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0 | SOR0_CLK_SEL1); } void sor_clock_start(void) { /* uses PLLP, has a non-standard bit layout. */ - setbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0); + setbits32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0); } static void init_pll(u32 index, u32 osc) @@ -280,13 +280,13 @@ static void init_pll(u32 index, u32 osc) /* Set Lock bit if needed. */ if (pll_reg->lock_enb_val) - setbits_le32(pll_reg->lock_enb_reg, pll_reg->lock_enb_val); + setbits32(pll_reg->lock_enb_reg, pll_reg->lock_enb_val); /* Set KCP/KVCO if needed. */ if (pll_reg->kcp_kvco_reg) - setbits_le32(pll_reg->kcp_kvco_reg, - pll->kcp << pll_reg->kcp_shift | - pll->kvco << pll_reg->kvco_shift); + setbits32(pll_reg->kcp_kvco_reg, + pll->kcp << pll_reg->kcp_shift | + pll->kvco << pll_reg->kvco_shift); /* Enable PLL and take it back out of BYPASS */ write32(pll_reg->base_reg, dividers | PLL_BASE_ENABLE); @@ -300,10 +300,10 @@ static void init_pll(u32 index, u32 osc) static void init_pllc(u32 osc) { /* Clear PLLC reset */ - clrbits_le32(CLK_RST_REG(pllc_misc), PLLC_MISC_RESET); + clrbits32(CLK_RST_REG(pllc_misc), PLLC_MISC_RESET); /* Clear PLLC IDDQ */ - clrbits_le32(CLK_RST_REG(pllc_misc_1), PLLC_MISC_1_IDDQ); + clrbits32(CLK_RST_REG(pllc_misc_1), PLLC_MISC_1_IDDQ); /* Max out the AVP clock before everything else (need PLLC for that). */ init_pll(PLLC_INDEX, osc); @@ -316,7 +316,7 @@ static void init_pllc(u32 osc) static void init_pllu(u32 osc) { /* Clear PLLU IDDQ */ - clrbits_le32(CLK_RST_REG(pllu_misc), PLLU_MISC_IDDQ); + clrbits32(CLK_RST_REG(pllu_misc), PLLU_MISC_IDDQ); /* Wait 5 us */ udelay(5); @@ -508,13 +508,13 @@ void clock_external_output(int clk_id) { switch (clk_id) { case 1: - setbits_le32(&pmc->clk_out_cntrl, 1 << 2); + setbits32(&pmc->clk_out_cntrl, 1 << 2); break; case 2: - setbits_le32(&pmc->clk_out_cntrl, 1 << 10); + setbits32(&pmc->clk_out_cntrl, 1 << 10); break; case 3: - setbits_le32(&pmc->clk_out_cntrl, 1 << 18); + setbits32(&pmc->clk_out_cntrl, 1 << 18); break; default: printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n", @@ -555,7 +555,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 kvco, u32 kcp, (p << PLL_BASE_DIVP_SHIFT)); write32(CLK_RST_REG(pllm_base), base); - setbits_le32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE); + setbits32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE); /* stable_time is required, before we can start to check lock. */ udelay(stable_time); @@ -587,8 +587,8 @@ void clock_init(void) { u32 osc = clock_get_osc_bits(); /* clk_m = osc/2 */ - clrsetbits_le32(CLK_RST_REG(spare_reg0), CLK_M_DIVISOR_MASK, - CLK_M_DIVISOR_BY_2); + clrsetbits32(CLK_RST_REG(spare_reg0), CLK_M_DIVISOR_MASK, + CLK_M_DIVISOR_BY_2); /* TIMERUS needs to be adjusted for new 19.2MHz CLK_M rate */ write32((void *)TEGRA_TMRUS_BASE + TIMERUS_USEC_CFG, @@ -608,7 +608,7 @@ void clock_init(void) SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT); /* Change the oscillator drive strength (from U-Boot -- why?) */ - clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, + clrsetbits32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK, OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); /* @@ -616,11 +616,11 @@ void clock_init(void) * "should update same value in PMC_OSC_EDPD_OVER XOFS * field for warmboot " */ - clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, - OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); + clrsetbits32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK, + OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ - clrbits_le32(CLK_RST_REG(pllx_misc3), PLLX_IDDQ_MASK); + clrbits32(CLK_RST_REG(pllx_misc3), PLLX_IDDQ_MASK); /* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */ write32(CLK_RST_REG(pllp_outa), diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c index 8d74bd3fb6..4f236c09e3 100644 --- a/src/soc/nvidia/tegra210/cpu.c +++ b/src/soc/nvidia/tegra210/cpu.c @@ -58,7 +58,7 @@ void cpu_prepare_startup(void *entry_64) */ write32(&sb->sb_aa64_reset_low, (uintptr_t)entry_64); - setbits_le32(&sb->sb_aa64_reset_low, 1); + setbits32(&sb->sb_aa64_reset_low, 1); write32(&sb->sb_aa64_reset_high, 0); } diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 75376d98f0..2984abec97 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -94,7 +94,7 @@ struct apb_dma_channel * const dma_claim(void) * Set global enable bit, otherwise register access to channel * DMA registers will not be possible. */ - setbits_le32(&apb_dma->command, APB_COMMAND_GEN); + setbits32(&apb_dma->command, APB_COMMAND_GEN); for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { regs = apb_dma_channels[i].regs; @@ -134,7 +134,7 @@ void dma_release(struct apb_dma_channel * const channel) return; } - clrbits_le32(&apb_dma->command, APB_COMMAND_GEN); + clrbits32(&apb_dma->command, APB_COMMAND_GEN); } int dma_start(struct apb_dma_channel * const channel) @@ -142,7 +142,7 @@ int dma_start(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Set ENB bit for this channel */ - setbits_le32(®s->csr, APB_CSR_ENB); + setbits32(®s->csr, APB_CSR_ENB); return 0; } @@ -152,7 +152,7 @@ int dma_stop(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Clear ENB bit for this channel */ - clrbits_le32(®s->csr, APB_CSR_ENB); + clrbits32(®s->csr, APB_CSR_ENB); return 0; } diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 6d8c3386a0..8c4530c027 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -320,8 +320,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div, printk(BIOS_ERR, "%s clock divisor overflow!", name); hlt(); } - clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, - src << CLK_SOURCE_SHIFT | div); + clrsetbits32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + src << CLK_SOURCE_SHIFT | div); } #define get_i2c_clk_div(src, freq) \ diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index e1d91fd0f2..ce615476e6 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -34,7 +34,7 @@ static void sdram_patch(uintptr_t addr, uint32_t value) static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) { - clrsetbits_le32(addr, mask, (value & mask)); + clrsetbits32(addr, mask, (value & mask)); } static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs) @@ -82,15 +82,15 @@ static void sdram_start_clocks(const struct sdram_params *param, u32 clk_source_emc = param->EmcClockSource; /* Enable the clocks for EMC and MC */ - setbits_le32(&clk_rst->clk_enb_h_set, (1 << 25)); // ENB_EMC - setbits_le32(&clk_rst->clk_enb_h_set, (1 << 0)); // ENB_MC + setbits32(&clk_rst->clk_enb_h_set, (1 << 25)); // ENB_EMC + setbits32(&clk_rst->clk_enb_h_set, (1 << 0)); // ENB_MC if ((clk_source_emc >> EMC_2X_CLK_SRC_SHIFT) != PLLM_UD) - setbits_le32(&clk_rst->clk_enb_x_set, CLK_ENB_EMC_DLL); + setbits32(&clk_rst->clk_enb_x_set, CLK_ENB_EMC_DLL); /* Remove the EMC and MC controllers from reset */ - clrbits_le32(&clk_rst->rst_dev_h, (1 << 25)); // SWR_EMC - clrbits_le32(&clk_rst->rst_dev_h, (1 << 0)); // SWR_MC + clrbits32(&clk_rst->rst_dev_h, (1 << 25)); // SWR_EMC + clrbits32(&clk_rst->rst_dev_h, (1 << 0)); // SWR_MC clk_source_emc |= (is_same_freq << 16); @@ -818,9 +818,9 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, (param->EmcPinGpio << EMC_PIN_GPIO_SHIFT); write32(®s->pin, val); - clrbits_le32(®s->pin, - (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | - EMC_PIN_CKE_MASK)); + clrbits32(®s->pin, + (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | + EMC_PIN_CKE_MASK)); /* * Assert dummy read of PIN register to ensure above write goes * through. Wait an additional 200us here as per NVIDIA. @@ -829,7 +829,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, udelay(param->EmcPinExtraWait + 200); /* Deassert reset */ - setbits_le32(®s->pin, EMC_PIN_RESET_INACTIVE); + setbits32(®s->pin, EMC_PIN_RESET_INACTIVE); /* * Assert dummy read of PIN register to ensure above write goes @@ -840,7 +840,7 @@ static void sdram_set_clock_enable_signal(const struct sdram_params *param, } /* Enable clock enable signal */ - setbits_le32(®s->pin, EMC_PIN_CKE_NORMAL); + setbits32(®s->pin, EMC_PIN_CKE_NORMAL); /* Dummy read of PIN register to ensure final write goes through */ dummy |= read32(®s->pin); @@ -1005,7 +1005,7 @@ static void sdram_enable_arbiter(const struct sdram_params *param) /* TODO(hungte) Move values here to standalone header file. */ uint32_t *ahb_arbitration_xbar_ctrl = (uint32_t *)(AHB_ARB_XBAR_CTRL); - setbits_le32(ahb_arbitration_xbar_ctrl, + setbits32(ahb_arbitration_xbar_ctrl, param->AhbArbitrationXbarCtrlMemInitDone << 16); } diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 5a065ba199..b0142a4bea 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -188,13 +188,13 @@ struct tegra_spi_channel *tegra_spi_init(unsigned int bus) return NULL; /* software drives chip-select, set value to high */ - setbits_le32(&spi->regs->command1, + setbits32(&spi->regs->command1, SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); /* 8-bit transfers, unpacked mode, most significant bit first */ - clrbits_le32(&spi->regs->command1, + clrbits32(&spi->regs->command1, SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); - setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); return spi; } @@ -263,7 +263,7 @@ static void dump_fifo_status(struct tegra_spi_channel *spi) static void clear_fifo_status(struct tegra_spi_channel *spi) { - clrbits_le32(&spi->regs->fifo_status, + clrbits32(&spi->regs->fifo_status, SPI_FIFO_STATUS_ERR | SPI_FIFO_STATUS_TX_FIFO_OVF | SPI_FIFO_STATUS_TX_FIFO_UNR | @@ -374,7 +374,7 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, */ write32(&spi->regs->dma_blk, todo - 1); - setbits_le32(&spi->regs->command1, enable_mask); + setbits32(&spi->regs->command1, enable_mask); if (dir == SPI_SEND) { unsigned int to_fifo = bytes; @@ -390,7 +390,7 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, static void tegra_spi_pio_start(struct tegra_spi_channel *spi) { - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); /* * Need to stabilize other reg bit before GO bit set. * @@ -403,7 +403,7 @@ static void tegra_spi_pio_start(struct tegra_spi_channel *spi) * enabling pio or dma. */ udelay(2); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + setbits32(&spi->regs->command1, SPI_CMD1_GO); /* Need to wait a few cycles before command1 register is read */ udelay(1); /* Make sure the write to command1 completes. */ @@ -421,7 +421,7 @@ static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) { u8 *p = spi->in_buf; - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); ASSERT(rx_fifo_count(spi) == spi_byte_count(spi)); @@ -447,19 +447,19 @@ static void setup_dma_params(struct tegra_spi_channel *spi, struct apb_dma_channel *dma) { /* APB bus width = 8-bits, address wrap for each word */ - clrbits_le32(&dma->regs->apb_seq, + clrbits32(&dma->regs->apb_seq, APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT); /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), * no address wrapping */ - clrsetbits_le32(&dma->regs->ahb_seq, + clrsetbits32(&dma->regs->ahb_seq, (AHB_BURST_MASK << AHB_BURST_SHIFT), 4 << AHB_BURST_SHIFT); /* Set ONCE mode to transfer one "block" at a time (64KB) and enable * flow control. */ - clrbits_le32(&dma->regs->csr, + clrbits32(&dma->regs->csr, APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT); - setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | + setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW | (spi->req_sel << APB_CSR_REQ_SEL_SHIFT)); } @@ -496,7 +496,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_out->regs->apb_ptr, (uintptr_t) & spi->regs->tx_fifo); write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); - setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR); + setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_out); write32(&spi->dma_out->regs->wcount, wcount); } else { @@ -510,7 +510,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, write32(&spi->dma_in->regs->apb_ptr, (uintptr_t)&spi->regs->rx_fifo); write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf); - clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR); + clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR); setup_dma_params(spi, spi->dma_in); write32(&spi->dma_in->regs->wcount, wcount); } @@ -527,7 +527,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) * (set bit to clear) between each transaction. Otherwise the next * transaction does not start. */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits32(&spi->regs->trans_status, SPI_STATUS_RDY); struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; @@ -539,21 +539,21 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ if (spi->dma_out) { /* Enable secure access for the channel. */ - setbits_le32(&apb_dma->security_reg, + setbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_out->num)); - clrsetbits_le32(&spi->regs->dma_ctl, + clrsetbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT, 1 << SPI_DMA_CTL_TX_TRIG_SHIFT); - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_TX_EN); } if (spi->dma_in) { /* Enable secure access for the channel. */ - setbits_le32(&apb_dma->security_reg, + setbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_in->num)); - clrsetbits_le32(&spi->regs->dma_ctl, + clrsetbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT, 1 << SPI_DMA_CTL_RX_TRIG_SHIFT); - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + setbits32(&spi->regs->command1, SPI_CMD1_RX_EN); } /* @@ -562,7 +562,7 @@ static void tegra_spi_dma_start(struct tegra_spi_channel *spi) */ if (spi->dma_out) dma_start(spi->dma_out); - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); if (spi->dma_in) dma_start(spi->dma_in); @@ -583,9 +583,9 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) dma_busy(spi->dma_in)) ; dma_stop(spi->dma_in); - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN); /* Disable secure access for the channel. */ - clrbits_le32(&apb_dma->security_reg, + clrbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_in->num)); dma_release(spi->dma_in); } @@ -596,10 +596,10 @@ static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || dma_busy(spi->dma_out)) ; - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN); dma_stop(spi->dma_out); /* Disable secure access for the channel. */ - clrbits_le32(&apb_dma->security_reg, + clrbits32(&apb_dma->security_reg, SECURITY_EN_BIT(spi->dma_out->num)); dma_release(spi->dma_out); } diff --git a/src/soc/qualcomm/ipq40xx/blsp.c b/src/soc/qualcomm/ipq40xx/blsp.c index 75618c2461..099dc6e2c1 100644 --- a/src/soc/qualcomm/ipq40xx/blsp.c +++ b/src/soc/qualcomm/ipq40xx/blsp.c @@ -47,7 +47,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id) return BLSP_UNSUPPORTED; /* Configure Mini core to I2C core */ - clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); + clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); return BLSP_SUCCESS; } diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c index e3d60e4749..bd1345e4ac 100644 --- a/src/soc/qualcomm/ipq40xx/clock.c +++ b/src/soc/qualcomm/ipq40xx/clock.c @@ -59,7 +59,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, 2 << 12); /* 13:12 Mode = Dual Edge */ /* Trigger update */ - setbits_le32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1); + setbits32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1); /* Wait for update */ for (i = 0; i < CLOCK_UPDATE_DELAY; i++) { @@ -71,7 +71,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m, } /* Please refer to the comments in blsp_i2c_clock_config() */ - setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); + setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); } /** @@ -154,7 +154,7 @@ int blsp_i2c_clock_config(blsp_qup_id_t id) * the same bits is harmless. Hence repeating them here should be ok. * This will ensure root and branch clocks remain on. */ - setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); + setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP); /* Src Sel 1 (fepll 200), Src Div 10.5 */ write32(clk[id].cfg, (1u << 8) | (20u << 0)); diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h index 930c912ee6..e4b613f7dc 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h @@ -47,8 +47,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v,a) write32((void *)a, v) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) +#define clrsetbits32_i(addr, clear, set) \ + clrsetbits32(((void *)(addr)), (clear), (set)) #define GCC_CLK_CTL_REG ((void *)0x01800000u) #define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index b68e1cb864..3b0d63603d 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -240,7 +240,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * Configure Mini core to SPI core with Input Output enabled, * SPI master, N = 8 bits */ - clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | QUP_CONF_INPUT_MSK | QUP_CONF_OUTPUT_MSK | QUP_CONF_N_MASK, @@ -253,7 +253,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * Configure Input first SPI protocol, * SPI master mode and no loopback */ - clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | SPI_CONFIG_NO_SLAVE_OPER_MSK, SPI_CONFIG_NO_LOOP_BACK | SPI_CONFIG_NO_SLAVE_OPER); @@ -273,7 +273,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * INPUT_MODE = Block Mode * OUTPUT MODE = Block Mode */ - clrsetbits_le32(ds->regs->qup_io_modes, + clrsetbits32(ds->regs->qup_io_modes, QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | QUP_IO_MODES_INPUT_MODE_MSK | QUP_IO_MODES_OUTPUT_MODE_MSK, @@ -320,10 +320,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert) struct ipq_spi_slave *ds = to_ipq_spi(slave); if (assert) - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); else - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); return; @@ -385,18 +385,18 @@ static void enable_io_config(struct ipq_spi_slave *ds, { if (write_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); } if (read_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); } diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 15ea852ae8..5b7469c3fb 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -23,7 +23,7 @@ */ void uart_pll_vote_clk_enable(unsigned int clk_dummy) { - setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8)); + setbits32(BB_PLL_ENA_SC0_REG, BIT(8)); if (!clk_dummy) while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0); @@ -39,11 +39,11 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, unsigned int n) { /* Assert MND reset. */ - setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); + setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); /* Program M and D values. */ write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n)); /* Deassert MND reset. */ - clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); + clrbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); } /** @@ -53,7 +53,7 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, */ static void uart_branch_clk_enable_reg(unsigned int gsbi_port) { - setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); + setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); } /** @@ -100,7 +100,7 @@ static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n, */ static void uart_set_gsbi_clk(unsigned int gsbi_port) { - setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); + setbits32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); } /** diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h index 76fd353bca..d501a81b39 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h @@ -46,8 +46,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v,a) write32((void *)a, v) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) +#define clrsetbits32_i(addr, clear, set) \ + clrsetbits32(((void *)(addr)), (clear), (set)) #define MSM_CLK_CTL_BASE ((void *)0x00900000) diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 183b33c20a..e2467b9ffd 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -307,7 +307,7 @@ static void gsbi_pin_config(unsigned int port_num, int cs_num) unsigned int gpio; unsigned int i; /* Hold the GSBIn (core_num) core in reset */ - clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)), + clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)), GSBI1_RESET_MSK, GSBI1_RESET); /* @@ -348,11 +348,11 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) int ret; /* Hold the GSBIn (core_num) core in reset */ - clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI1_RESET_MSK, GSBI1_RESET); /* Disable GSBIn (core_num) QUP core clock branch */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, QUP_CLK_BRANCH_DIS); ret = check_qup_clk_state(ds->slave.bus, 1); @@ -363,41 +363,41 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) } /* Disable M/N:D counter and hold M/N:D counter in reset */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK), + clrsetbits32_i(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK), (MNCNTR_RST_ENA | MNCNTR_DIS)); /* Disable GSBIn (core_num) QUP core clock root */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS); + clrsetbits32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS); - clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK, GSBIn_PLL_SRC_PLL8); - clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK, (0 << GSBI_PRE_DIV_SEL_SHFT)); /* Program M/N:D values for GSBIn_QUP_APPS_CLK @50MHz */ - clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK, + clrsetbits32_i(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK, (0x01 << GSBI_M_VAL_SHFT)); - clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK, + clrsetbits32_i(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK, (0xF7 << GSBI_D_VAL_SHFT)); - clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK, (0xF8 << GSBI_N_VAL_SHFT)); /* Set MNCNTR_MODE = 0: Bypass mode */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK, MNCNTR_MODE_DUAL_EDGE); /* De-assert the M/N:D counter reset */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS); - clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN); + clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS); + clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN); /* * Enable the GSBIn (core_num) QUP core clock root. * Keep MND counter disabled */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA); + clrsetbits32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA); /* Enable GSBIn (core_num) QUP core clock branch */ - clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, + clrsetbits32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK, QUP_CLK_BRANCH_ENA); ret = check_qup_clk_state(ds->slave.bus, 0); @@ -409,7 +409,7 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) } /* Enable GSBIn (core_num) core clock branch */ - clrsetbits_le32_i(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits32_i(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI_CLK_BRANCH_ENA_MSK, GSBI_CLK_BRANCH_ENA); ret = check_hclk_state(ds->slave.bus, 0); @@ -420,7 +420,7 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds) } /* Release GSBIn (core_num) core from reset */ - clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), + clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)), GSBI1_RESET_MSK, 0); udelay(50); @@ -541,14 +541,14 @@ static int spi_hw_init(struct ipq_spi_slave *ds) return ret; /* Configure GSBI_CTRL register to set protocol_mode to SPI:011 */ - clrsetbits_le32_i(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK, + clrsetbits32_i(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK, PROTOCOL_CODE_SPI); /* * Configure Mini core to SPI core with Input Output enabled, * SPI master, N = 8 bits */ - clrsetbits_le32_i(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK | + clrsetbits32_i(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK | SPI_QUP_CONF_INPUT_MSK | SPI_QUP_CONF_OUTPUT_MSK | SPI_BIT_WORD_MSK), @@ -561,7 +561,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * Configure Input first SPI protocol, * SPI master mode and no loopback */ - clrsetbits_le32_i(ds->regs->spi_config, (LOOP_BACK_MSK | + clrsetbits32_i(ds->regs->spi_config, (LOOP_BACK_MSK | SLAVE_OPERATION_MSK), (NO_LOOP_BACK | SLAVE_OPERATION)); @@ -581,7 +581,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) * INPUT_MODE = Block Mode * OUTPUT MODE = Block Mode */ - clrsetbits_le32_i(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK | + clrsetbits32_i(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK | INPUT_BLOCK_MODE_MSK | OUTPUT_BLOCK_MODE_MSK), (OUTPUT_BIT_SHIFT_EN | @@ -707,7 +707,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, * Let's do the write side of the transaction first. Enable output * FIFO. */ - clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK, + clrsetbits32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK, SPI_QUP_CONF_OUTPUT_ENA); while (out_bytes) { @@ -729,7 +729,7 @@ spi_receive: goto out; /* Enable input FIFO */ - clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK, + clrsetbits32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK, SPI_QUP_CONF_INPUT_ENA); while (in_bytes) { diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c index 35285cd0d5..003bc7bf0b 100644 --- a/src/soc/qualcomm/ipq806x/usb.c +++ b/src/soc/qualcomm/ipq806x/usb.c @@ -127,9 +127,9 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) udelay(5); - clrbits_le32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */ - clrbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ - clrbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + clrbits32(&dwc3->ctl, 0x1 << 11); /* deassert core soft reset */ + clrbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + clrbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ } static void setup_phy(struct usb_qc_phy *phy) @@ -164,7 +164,7 @@ static void setup_phy(struct usb_qc_phy *phy) write32(&phy->general_cfg, 0x1 << 2); /* set XHCI 1.00 compliance */ udelay(5); - clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ + clrbits32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */ } static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data) @@ -206,7 +206,7 @@ static void tune_phy(struct usb_qc_phy *phy) void setup_usb_host1(void) { printk(BIOS_INFO, "Setting up USB HOST1 controller...\n"); - setbits_le32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */ + setbits32(tcsr_usb_sel, 1 << 0); /* Select DWC3 controller */ setup_phy(usb_host1_phy); setup_dwc3(usb_host1_dwc3); tune_phy(usb_host1_phy); @@ -215,7 +215,7 @@ void setup_usb_host1(void) void setup_usb_host2(void) { printk(BIOS_INFO, "Setting up USB HOST2 controller...\n"); - setbits_le32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */ + setbits32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */ setup_phy(usb_host2_phy); setup_dwc3(usb_host2_dwc3); tune_phy(usb_host2_phy); diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c index f185ea388a..42dc28d16c 100644 --- a/src/soc/qualcomm/qcs405/blsp.c +++ b/src/soc/qualcomm/qcs405/blsp.c @@ -59,7 +59,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id) return BLSP_ID_ERROR; /* Configure Mini core to I2C core */ - clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); + clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); return BLSP_SUCCESS; } diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 37fd2c2098..da2e8a4603 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -96,7 +96,7 @@ struct clock_config spi_cfg[] = { static int clock_configure_gpll0(void) { /* Keep existing GPLL0 configuration, in RUN mode @800Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_AUX2_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_AUX_SHFT | @@ -144,7 +144,7 @@ static int clock_configure(struct qcs405_clock *clk, clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -159,7 +159,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)); @@ -171,7 +171,7 @@ static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -184,7 +184,7 @@ static int clock_disable(void *cbcr_addr) { /* Set clock enable bit */ - clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + clrbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); return 0; } @@ -193,9 +193,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset) struct qcs405_bcr *bcr = bcr_addr; if (reset) - setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c index fc58fae7ff..19027c32bb 100644 --- a/src/soc/qualcomm/qcs405/gpio.c +++ b/src/soc/qualcomm/qcs405/gpio.c @@ -78,9 +78,9 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) gpio_configure(gpio, GPIO_FUNC_GPIO, pull, GPIO_2MA, GPIO_DISABLE); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + clrsetbits32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + clrsetbits32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT); } diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h index 2ed3e10f76..7d948ec46e 100644 --- a/src/soc/qualcomm/qcs405/include/soc/iomap.h +++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h @@ -48,8 +48,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v, a) write32((void *)a, v) -#define clrsetbits_le32_i(addr, clear, set) \ - clrsetbits_le32(((void *)(addr)), (clear), (set)) +#define clrsetbits32_i(addr, clear, set) \ + clrsetbits32(((void *)(addr)), (clear), (set)) #define GCC_CLK_CTL_REG ((void *)0x01800000u) #define MSM_CLK_CTL_BASE GCC_CLK_CTL_REG diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 827448ce91..f621778f65 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -247,10 +247,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert) { struct qcs_spi_slave *ds = to_qcs_spi(slave); if (assert) - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN); else - clrsetbits_le32(ds->regs->io_control, + clrsetbits32(ds->regs->io_control, SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS); } @@ -275,7 +275,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds) * Configure Mini core to SPI core with Input Output enabled, * SPI master, N = 8 bits */ - clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | + clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK | QUP_CONF_INPUT_MSK | QUP_CONF_OUTPUT_MSK | QUP_CONF_N_MASK, @@ -288,7 +288,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds) * Configure Input first SPI protocol, * SPI master mode and no loopback */ - clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | + clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK | SPI_CONFIG_NO_SLAVE_OPER_MSK, SPI_CONFIG_NO_LOOP_BACK | SPI_CONFIG_NO_SLAVE_OPER); @@ -308,7 +308,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds) * INPUT_MODE = Block Mode * OUTPUT MODE = Block Mode */ - clrsetbits_le32(ds->regs->qup_io_modes, + clrsetbits32(ds->regs->qup_io_modes, QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK | QUP_IO_MODES_INPUT_MODE_MSK | QUP_IO_MODES_OUTPUT_MODE_MSK, @@ -433,18 +433,18 @@ static void enable_io_config(struct qcs_spi_slave *ds, { if (write_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT); } if (read_cnt) { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA); } else { - clrsetbits_le32(ds->regs->qup_config, + clrsetbits32(ds->regs->qup_config, QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT); } } diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index a94973ff2b..7ddfaa231e 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -183,16 +183,16 @@ static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3) static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_INFO, "Configure USB in Host mode\n"); } @@ -213,10 +213,10 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) if (port == HSUSB_SS_PORT_0) { /* Set PHY reset. */ - setbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + setbits32(&dwc3->usb2_phy_bcr, BIT(1)); udelay(15); /* Clear PHY reset. */ - clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1)); + clrbits32(&dwc3->usb2_phy_bcr, BIT(1)); } else { clock_reset_bcr(dwc3->usb2_phy_bcr, 1); udelay(15); @@ -229,13 +229,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) if (port == HSUSB_SS_PORT_0) { /* Set PHY POR reset. */ - setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + setbits32(&dwc3->usb2_phy_por_bcr, BIT(0)); val = read8(&dwc3->usb2_phy_dig->ctrl_common0); val &= ~(0x4); write8(&dwc3->usb2_phy_dig->ctrl_common0, val); udelay(20); /* Clear PHY POR reset. */ - clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0)); + clrbits32(&dwc3->usb2_phy_por_bcr, BIT(0)); } else { clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1); val = read8(&dwc3->usb2_phy_dig->ctrl_common0); @@ -254,13 +254,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data) */ /* Configure dwc3 to use UTMI clock as PIPE clock not present */ - setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_DIS); udelay(2); - setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); udelay(3); - clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, + clrbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg, PIPE_UTMI_CLK_DIS); printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index 9f3b722e31..ad89f85011 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include <arch/mmio.h> #include <assert.h> #include <delay.h> +#include <device/mmio.h> #include <timer.h> #include <timestamp.h> #include <types.h> @@ -86,9 +86,9 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) gpio_configure(gpio, GPIO_FUNC_GPIO, pull, GPIO_2MA, GPIO_OUTPUT_DISABLE); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + clrsetbits32(®s->intr_cfg, GPIO_INTR_DECT_CTL_MASK << GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); - clrsetbits_le32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + clrsetbits32(®s->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE << GPIO_INTR_RAW_STATUS_EN_SHIFT); } diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index e55495b86e..f3b34cf68a 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -66,7 +66,7 @@ struct clock_config qspi_core_cfg[] = { static int clock_configure_gpll0(void) { /* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */ - setbits_le32(&gcc->gpll0.user_ctl, + setbits32(&gcc->gpll0.user_ctl, 1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT | 1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT); @@ -76,7 +76,7 @@ static int clock_configure_gpll0(void) static int clock_configure_mnd(struct sdm845_clock *clk, uint32_t m, uint32_t n, uint32_t d_2) { - setbits_le32(&clk->rcg.cfg, + setbits32(&clk->rcg.cfg, RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK); @@ -110,7 +110,7 @@ static int clock_configure(struct sdm845_clock *clk, clk_cfg[idx].d_2); /* Commit config to RCG*/ - setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); + setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); return 0; } @@ -125,7 +125,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr, { /* Set clock vote bit */ - setbits_le32(vote_addr, BIT(vote_bit)); + setbits32(vote_addr, BIT(vote_bit)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -138,7 +138,7 @@ static int clock_enable(void *cbcr_addr) { /* Set clock enable bit */ - setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); + setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT)); /* Ensure clock is enabled */ while (clock_is_off(cbcr_addr)) @@ -169,9 +169,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset) struct sdm845_bcr *bcr = bcr_addr; if (reset) - setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); else - clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); + clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT)); return 0; } diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c index 8e2b9119ae..56da28e44d 100644 --- a/src/soc/qualcomm/sdm845/usb.c +++ b/src/soc/qualcomm/sdm845/usb.c @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#include <arch/mmio.h> #include <stdlib.h> #include <console/console.h> #include <delay.h> +#include <device/mmio.h> #include <soc/usb.h> #include <soc/clock.h> #include <soc/addressmap.h> @@ -725,7 +725,7 @@ static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) * tune parameters. */ if (tune_val) - clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + clrsetbits32(&dwc3->qusb_phy_dig->tune1, PORT_TUNE1_MASK, tune_val << 4); } @@ -762,7 +762,7 @@ static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) { /* PWR_CTRL: set the power down bit to disable the PHY */ - setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_pll->analog_controls_two, QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); @@ -782,7 +782,7 @@ static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) tune_phy(dwc3, dwc3->qusb_phy_dig); /* PWR_CTRL1: Clear the power down bit to enable the PHY */ - clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); write32(&dwc3->qusb_phy_dig->debug_ctrl2, DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); @@ -848,7 +848,7 @@ static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) static void setup_dwc3(struct usb_dwc3 *dwc3) { /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ - clrsetbits_le32(&dwc3->usb3pipectl, + clrsetbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_DELAYP1TRANS, DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); @@ -858,18 +858,18 @@ static void setup_dwc3(struct usb_dwc3 *dwc3) * 2. Set USBTRDTIM to the corresponding value * according to the UTMI+ PHY interface. */ - clrsetbits_le32(&dwc3->usb2phycfg, + clrsetbits32(&dwc3->usb2phycfg, (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | DWC3_GUSB2PHYCFG_PHYIF_MASK), (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | DWC3_GCTL_DISSCRAMBLE), DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); /* configure controller in Host mode */ - clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); printk(BIOS_SPEW, "Configure USB in Host mode\n"); } diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index ea0930a058..18afc3a50a 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -97,7 +97,7 @@ static void rk_edp_init_interrupt(struct rk_edp *edp) static void rk_edp_enable_sw_function(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, SW_FUNC_EN_N); + clrbits32(&edp->regs->func_en_1, SW_FUNC_EN_N); } static int rk_edp_get_pll_lock_status(struct rk_edp *edp) @@ -116,7 +116,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) write32(&edp->regs->common_int_sta_1, PLL_LOCK_CHG); - clrbits_le32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); + clrbits32(&edp->regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -128,7 +128,7 @@ static void rk_edp_init_analog_func(struct rk_edp *edp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | + clrbits32(&edp->regs->func_en_2, SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N | SSC_FUNC_EN_N); } @@ -139,20 +139,20 @@ static void rk_edp_init_aux(struct rk_edp *edp) write32(&edp->regs->dp_int_sta, AUX_FUNC_EN_N); /* Disable AUX channel module */ - setbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + setbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ write32(&edp->regs->aux_ch_defer_dtl, DEFER_CTRL_EN | DEFER_COUNT(1)); /* Enable AUX channel module */ - clrbits_le32(&edp->regs->func_en_2, AUX_FUNC_EN_N); + clrbits32(&edp->regs->func_en_2, AUX_FUNC_EN_N); } static int rk_edp_aux_enable(struct rk_edp *edp) { struct stopwatch sw; - setbits_le32(&edp->regs->aux_ch_ctl_2, AUX_EN); + setbits32(&edp->regs->aux_ch_ctl_2, AUX_EN); stopwatch_init_msecs_expire(&sw, 20); do { if (!(read32(&edp->regs->aux_ch_ctl_2) & AUX_EN)) @@ -698,7 +698,7 @@ static int rk_edp_read_bytes_from_i2c(struct rk_edp *edp, write32(&edp->regs->buf_data_ctl, val); /* Set normal AUX CH command */ - clrbits_le32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); + clrbits32(&edp->regs->aux_ch_ctl_2, ADDR_ONLY); /* * If Rx sends defer, Tx sends only reads @@ -816,7 +816,7 @@ static void rk_edp_init_video(struct rk_edp *edp) static void rk_edp_config_video_slave_mode(struct rk_edp *edp) { - clrbits_le32(&edp->regs->func_en_1, + clrbits32(&edp->regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N); } @@ -828,7 +828,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, u32 val; if (type == REGISTER_M) { - setbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + setbits32(&edp->regs->sys_ctl_4, FIX_M_VID); val = m_value & 0xff; write32(&edp->regs->m_vid_0, val); val = (m_value >> 8) & 0xff; @@ -843,7 +843,7 @@ static void rk_edp_set_video_cr_mn(struct rk_edp *edp, val = (n_value >> 16) & 0xff; write32(&edp->regs->n_vid_2, val); } else { - clrbits_le32(&edp->regs->sys_ctl_4, FIX_M_VID); + clrbits32(&edp->regs->sys_ctl_4, FIX_M_VID); write32(&edp->regs->n_vid_0, 0x00); write32(&edp->regs->n_vid_1, 0x80); @@ -914,10 +914,10 @@ static int rk_edp_config_video(struct rk_edp *edp) rk_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0); /* For video bist, Video timing must be generated by register */ - clrbits_le32(&edp->regs->video_ctl_10, F_SEL); + clrbits32(&edp->regs->video_ctl_10, F_SEL); /* Disable video mute */ - clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); + clrbits32(&edp->regs->video_ctl_1, VIDEO_MUTE); return 0; } @@ -1000,7 +1000,7 @@ int rk_edp_prepare(void) int rk_edp_enable(void) { /* Enable video at next frame */ - setbits_le32(&rk_edp.regs->video_ctl_1, VIDEO_EN); + setbits32(&rk_edp.regs->video_ctl_1, VIDEO_EN); return rk_edp_is_video_stream_on(&rk_edp); } diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 3d7e1614e0..16ab385b03 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -24,16 +24,16 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr, - 1 << gpio.num, dir << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_ddr, + 1 << gpio.num, dir << gpio.num); } static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); if (is_pmu_gpio(gpio) && CONFIG(SOC_ROCKCHIP_RK3288)) - clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), - pull_val << (gpio.idx * 2)); + clrsetbits32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), + pull_val << (gpio.idx * 2)); else write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), pull_val << (gpio.idx * 2))); @@ -83,13 +83,13 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, enum gpio_pull pull) case IRQ_TYPE_LEVEL_LOW: break; } - clrsetbits_le32(&gpio_port[gpio.port]->int_polarity, - mask, int_polarity); - clrsetbits_le32(&gpio_port[gpio.port]->inttype_level, - mask, inttype_level); + clrsetbits32(&gpio_port[gpio.port]->int_polarity, + mask, int_polarity); + clrsetbits32(&gpio_port[gpio.port]->inttype_level, + mask, inttype_level); - setbits_le32(&gpio_port[gpio.port]->inten, mask); - clrbits_le32(&gpio_port[gpio.port]->intmask, mask); + setbits32(&gpio_port[gpio.port]->inten, mask); + clrbits32(&gpio_port[gpio.port]->intmask, mask); } int gpio_irq_status(gpio_t gpio) @@ -100,7 +100,7 @@ int gpio_irq_status(gpio_t gpio) if (!(int_status & mask)) return 0; - setbits_le32(&gpio_port[gpio.port]->porta_eoi, mask); + setbits32(&gpio_port[gpio.port]->porta_eoi, mask); return 1; } @@ -111,8 +111,8 @@ int gpio_get(gpio_t gpio) void gpio_set(gpio_t gpio, int value) { - clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, - !!value << gpio.num); + clrsetbits32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, + !!value << gpio.num); } void gpio_output(gpio_t gpio, int value) diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index e5da05e672..82fc2596c0 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -79,5 +79,5 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns) write32(&rk_pwm->pwm[id].pwm_period_hpr, period); write32(&rk_pwm->pwm[id].pwm_duty_lpr, duty); - setbits_le32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); + setbits32(&rk_pwm->pwm[id].pwm_ctrl, RK_PWM_ENABLE); } diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 0307e24d35..d91bae0eac 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -70,13 +70,13 @@ static struct rockchip_spi_slave *to_rockchip_spi(const struct spi_slave *slave) static void spi_cs_activate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - setbits_le32(®s->ser, 1); + setbits32(®s->ser, 1); } static void spi_cs_deactivate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; - clrbits_le32(®s->ser, 1); + clrbits32(®s->ser, 1); } static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable) @@ -141,8 +141,8 @@ void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) /* Rxd Sample Delay */ rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); assert(rsd <= 3); - clrsetbits_le32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, - rsd << SPI_RXDSD_OFFSET); + clrsetbits32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, + rsd << SPI_RXDSD_OFFSET); } static int spi_ctrlr_claim_bus(const struct spi_slave *slave) @@ -172,7 +172,7 @@ static int rockchip_spi_wait_till_not_busy(struct rockchip_spi *regs) static void set_tmod(struct rockchip_spi *regs, unsigned int tmod) { - clrsetbits_le32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, + clrsetbits32(®s->ctrlr0, SPI_TMOD_MASK << SPI_TMOD_OFFSET, tmod << SPI_TMOD_OFFSET); } @@ -275,9 +275,9 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, } mask = SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET; if (use_16bit) - clrbits_le32(®s->ctrlr0, mask); + clrbits32(®s->ctrlr0, mask); else - setbits_le32(®s->ctrlr0, mask); + setbits32(®s->ctrlr0, mask); /* Enable/disable transmitter and receiver as needed to * avoid sending or reading spurious bits. */ diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 9c70b78171..6e0ce4086c 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -60,7 +60,7 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) write32(&preg->win0_dsp_info, V_DSP_WIDTH(hactive - 1) | V_DSP_HEIGHT(vactive - 1)); - clrsetbits_le32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, + clrsetbits32(&preg->win0_color_key, M_WIN0_KEY_EN | M_WIN0_KEY_COLOR, V_WIN0_KEY_EN(0) | V_WIN0_KEY_COLOR(0)); @@ -89,10 +89,10 @@ void rkvop_prepare(u32 vop_id, const struct edid *edid) else lb_mode = LB_RGB_1280X8; - clrsetbits_le32(&preg->win0_ctrl0, - M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, - V_WIN0_LB_MODE(lb_mode) | - V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); + clrsetbits32(&preg->win0_ctrl0, + M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, + V_WIN0_LB_MODE(lb_mode) | + V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); } void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) @@ -111,34 +111,34 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) switch (mode) { case VOP_MODE_HDMI: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); dsp_out_mode = 15; break; case VOP_MODE_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_DUAL_MIPI: - clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, - V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); + clrsetbits32(&preg->sys_ctrl, M_ALL_OUT_EN, + V_MIPI_OUT_EN(1) | V_DUAL_MIPI_EN(1)); dsp_out_mode = 0; break; case VOP_MODE_EDP: default: - clrsetbits_le32(&preg->sys_ctrl, - M_ALL_OUT_EN, V_EDP_OUT_EN(1)); + clrsetbits32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_EDP_OUT_EN(1)); dsp_out_mode = 15; break; } - clrsetbits_le32(&preg->dsp_ctrl0, - M_DSP_OUT_MODE | M_DSP_VSYNC_POL | - M_DSP_HSYNC_POL, - V_DSP_OUT_MODE(dsp_out_mode) | - V_DSP_HSYNC_POL(edid->mode.phsync == '+') | - V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); + clrsetbits32(&preg->dsp_ctrl0, + M_DSP_OUT_MODE | M_DSP_VSYNC_POL | + M_DSP_HSYNC_POL, + V_DSP_OUT_MODE(dsp_out_mode) | + V_DSP_HSYNC_POL(edid->mode.phsync == '+') | + V_DSP_VSYNC_POL(edid->mode.pvsync == '+')); write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch)); diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index b4de270fc5..6569d295ea 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -250,8 +250,8 @@ static void hdmi_update_csc_coeffs(void) } } - clrsetbits_le32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, - csc_scale); + clrsetbits32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, + csc_scale); } static void hdmi_video_csc(void) @@ -261,8 +261,8 @@ static void hdmi_video_csc(void) /* configure the csc registers */ write32(&hdmi_regs->csc_cfg, interpolation); - clrsetbits_le32(&hdmi_regs->csc_scale, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); + clrsetbits32(&hdmi_regs->csc_scale, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); hdmi_update_csc_coeffs(); } @@ -281,18 +281,18 @@ static void hdmi_video_packetize(void) HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); write32(&hdmi_regs->vp_pr_cd, val); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); /* data from pixel repeater block */ vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | - HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | + HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, - 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, + 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); write32(&hdmi_regs->vp_remap, remap_size); @@ -300,23 +300,23 @@ static void hdmi_video_packetize(void) HDMI_VP_CONF_PP_EN_DISABLE | HDMI_VP_CONF_YCC422_EN_DISABLE; - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | - HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, - vp_conf); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | + HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, + vp_conf); - clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | - HDMI_VP_STUFF_YCC422_STUFFING_MASK, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); + clrsetbits32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | + HDMI_VP_STUFF_YCC422_STUFFING_MASK, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); - clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, - output_select); + clrsetbits32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, + output_select); } static inline void hdmi_phy_test_clear(u8 bit) { - clrsetbits_le32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, - bit << HDMI_PHY_TST0_TSTCLR_OFFSET); + clrsetbits32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, + bit << HDMI_PHY_TST0_TSTCLR_OFFSET); } static int hdmi_phy_wait_i2c_done(u32 msec) @@ -352,46 +352,46 @@ static void hdmi_phy_i2c_write(u16 data, u8 addr) static void hdmi_phy_enable_power(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, - enable << HDMI_PHY_CONF0_PDZ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, + enable << HDMI_PHY_CONF0_PDZ_OFFSET); } static void hdmi_phy_enable_tmds(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, - enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, + enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); } static void hdmi_phy_enable_spare(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, - enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, + enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); } static void hdmi_phy_gen2_pddq(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, - enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, + enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); } static void hdmi_phy_gen2_txpwron(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, - enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, + enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); } static void hdmi_phy_sel_data_en_pol(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, - HDMI_PHY_CONF0_SELDATAENPOL_MASK, - enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_SELDATAENPOL_MASK, + enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); } static void hdmi_phy_sel_interface_control(u8 enable) { - clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, - enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); + clrsetbits32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, + enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); } static int hdmi_phy_configure(u32 mpixelclock) @@ -723,8 +723,8 @@ static int hdmi_ddc_wait_i2c_done(int msec) static void hdmi_ddc_reset(void) { - clrsetbits_le32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, - HDMI_I2CM_SOFTRSTZ); + clrsetbits32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, + HDMI_I2CM_SOFTRSTZ); } static int hdmi_read_edid(int block, u8 *buff) @@ -737,7 +737,7 @@ static int hdmi_read_edid(int block, u8 *buff) /* set ddc i2c clk which devided from ddc_clk to 100khz */ write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); - clrsetbits_le32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, + clrsetbits32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV_STD_MODE); write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR); @@ -751,13 +751,13 @@ static int hdmi_read_edid(int block, u8 *buff) write32(&hdmi_regs->i2cmess, shift + 8 * n); if (block == 0) - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8, - HDMI_I2CM_OPT_RD8); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8, + HDMI_I2CM_OPT_RD8); else - clrsetbits_le32(&hdmi_regs->i2cm_operation, - HDMI_I2CM_OPT_RD8_EXT, - HDMI_I2CM_OPT_RD8_EXT); + clrsetbits32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8_EXT, + HDMI_I2CM_OPT_RD8_EXT); if (hdmi_ddc_wait_i2c_done(10)) { hdmi_ddc_reset(); diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 74038b078e..3305263458 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -522,14 +522,14 @@ static void phy_pctrl_reset(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; rkclk_ddr_reset(channel, 1, 1); udelay(1); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLSRST); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLSRST); udelay(10); rkclk_ddr_reset(channel, 1, 0); @@ -544,23 +544,23 @@ static void phy_dll_bypass_set(struct rk3288_ddr_publ_regs *ddr_publ_regs, int i; if (freq <= 250*MHz) { if (freq <= 150*MHz) - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); else - setbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - setbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + setbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + setbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + setbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + setbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } else { - clrbits_le32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); - clrbits_le32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); + clrbits32(&ddr_publ_regs->dllgcr, SBIAS_BYPASS); + clrbits32(&ddr_publ_regs->acdllcr, ACDLLCR_DLLDIS); for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[i].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->pir, PIR_DLLBYP); + clrbits32(&ddr_publ_regs->pir, PIR_DLLBYP); } } @@ -637,7 +637,7 @@ static void pctl_cfg(u32 channel, break; } - setbits_le32(&ddr_pctl_regs->scfg, 1); + setbits32(&ddr_pctl_regs->scfg, 1); } static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) @@ -668,33 +668,33 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) switch (sdram_params->dramtype) { case LPDDR3: - clrsetbits_le32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) + clrsetbits32(&ddr_publ_regs->pgcr, 0x1F, PGCR_DFTLMT(0) | PGCR_DFTCMP(0) | PGCR_DQSCFG(1) | PGCR_ITMDMD(0)); /* DDRMODE select LPDDR3 */ - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_LPDDR2_LPDDR3)); - clrsetbits_le32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, + clrsetbits32(&ddr_publ_regs->dxccr, DQSNRES_MSK | DQSRES_MSK, DQSRES_CFG(4) | DQSNRES_CFG(0xc)); i = TDQSCKMAX_VAL(read32(&ddr_publ_regs->dtpr[1])) - TDQSCK_VAL(read32(&ddr_publ_regs->dtpr[1])); - clrsetbits_le32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, + clrsetbits32(&ddr_publ_regs->dsgcr, DQSGE_MSK | DQSGX_MSK, DQSGE_CFG(i) | DQSGX_CFG(i)); break; case DDR3: - clrbits_le32(&ddr_publ_regs->pgcr, 0x1f); - clrsetbits_le32(&ddr_publ_regs->dcr, DDRMD_MSK, + clrbits32(&ddr_publ_regs->pgcr, 0x1f); + clrsetbits32(&ddr_publ_regs->dcr, DDRMD_MSK, DDRMD_CFG(DDRMD_DDR3)); break; } if (sdram_params->odt) { /*dynamic RTT enable */ for (i = 0; i < 4; i++) - setbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + setbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } else { /*dynamic RTT disable */ for (i = 0; i < 4; i++) - clrbits_le32(&ddr_publ_regs->datx8[i].dxgcr, + clrbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); } @@ -702,7 +702,7 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) static void phy_init(struct rk3288_ddr_publ_regs *ddr_publ_regs) { - setbits_le32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST + setbits32(&ddr_publ_regs->pir, PIR_INIT | PIR_DLLSRST | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & @@ -723,10 +723,10 @@ static void send_command(struct rk3288_ddr_pctl_regs *ddr_pctl_regs, u32 rank, static void memory_init(struct rk3288_ddr_publ_regs *ddr_publ_regs, u32 dramtype) { - setbits_le32(&ddr_publ_regs->pir, - (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP - | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC - | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + setbits32(&ddr_publ_regs->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); udelay(1); while ((read32(&ddr_publ_regs->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) != (PGSR_IDONE | PGSR_DLDONE)) @@ -775,42 +775,42 @@ static void set_bandwidth_ratio(u32 channel, u32 n) struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; if (n == 1) { - setbits_le32(&ddr_pctl_regs->ppcfg, 1); + setbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_SETBITS(1 << (8 + channel))); - setbits_le32(&msch_regs->ddrtiming, 1 << 31); + setbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte disable*/ - clrbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - clrbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + clrbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*disable DLL */ - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); } else { - clrbits_le32(&ddr_pctl_regs->ppcfg, 1); + clrbits32(&ddr_pctl_regs->ppcfg, 1); write32(&rk3288_grf->soc_con0, RK_CLRBITS(1 << (8 + channel))); - clrbits_le32(&msch_regs->ddrtiming, 1 << 31); + clrbits32(&msch_regs->ddrtiming, 1 << 31); /* Data Byte enable*/ - setbits_le32(&ddr_publ_regs->datx8[2].dxgcr, 1); - setbits_le32(&ddr_publ_regs->datx8[3].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[2].dxgcr, 1); + setbits32(&ddr_publ_regs->datx8[3].dxgcr, 1); /*enable DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLDIS); /* reset DLL */ - clrbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - clrbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + clrbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); udelay(10); - setbits_le32(&ddr_publ_regs->datx8[2].dxdllcr, + setbits32(&ddr_publ_regs->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - setbits_le32(&ddr_publ_regs->datx8[3].dxdllcr, + setbits32(&ddr_publ_regs->datx8[3].dxdllcr, DXDLLCR_DLLSRST); } - setbits_le32(&ddr_pctl_regs->dfistcfg0, 1 << 2); + setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2); } @@ -829,19 +829,19 @@ static int data_training(u32 channel, write32(&ddr_pctl_regs->trefi, 0); if (sdram_params->dramtype != LPDDR3) - setbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + setbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); rank = sdram_params->ch[channel].rank | 1; for (j = 0; j < ARRAY_SIZE(step); j++) { /* * trigger QSTRN and RVTRN * clear DTDONE status */ - setbits_le32(&ddr_publ_regs->pir, PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, PIR_CLRSR); /* trigger DTT */ - setbits_le32(&ddr_publ_regs->pir, - PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | - PIR_CLRSR); + setbits32(&ddr_publ_regs->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); udelay(1); /* wait echo byte DTDONE */ while ((read32(&ddr_publ_regs->datx8[0].dxgsr[0]) & rank) @@ -869,7 +869,7 @@ static int data_training(u32 channel, send_command(ddr_pctl_regs, rank, REF_CMD, 0); if (sdram_params->dramtype != LPDDR3) - clrbits_le32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); + clrbits32(&ddr_publ_regs->pgcr, PGCR_DQSCFG(1)); /* resume auto refresh */ write32(&ddr_pctl_regs->trefi, sdram_params->pctl_timing.trefi); @@ -928,9 +928,9 @@ static void dram_cfg_rbc(u32 chnum, struct rk3288_msch_regs *msch_regs = rk3288_msch[chnum]; if (sdram_params->ch[chnum].bk == 3) - clrsetbits_le32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); + clrsetbits32(&ddr_publ_regs->dcr, PDQ_MSK, PDQ_CFG(1)); else - clrbits_le32(&ddr_publ_regs->dcr, PDQ_MSK); + clrbits32(&ddr_publ_regs->dcr, PDQ_MSK); write32(&msch_regs->ddrconf, sdram_params->ddrconfig); } @@ -1029,8 +1029,8 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) * CS1, n=2 * CS0 & CS1, n = 3 */ - clrsetbits_le32(&ddr_publ_regs->pgcr, 0xF << 18, - (sdram_params->ch[channel].rank | 1) << 18); + clrsetbits32(&ddr_publ_regs->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); /* DS=40ohm,ODT=155ohm */ zqcr = ZDEN(1) | PU_ONDIE(0x2) | PD_ONDIE(0x2) | PU_OUTPUT(0x19) | PD_OUTPUT(0x19); diff --git a/src/soc/rockchip/rk3288/software_i2c.c b/src/soc/rockchip/rk3288/software_i2c.c index 8c439842c1..67fca1f624 100644 --- a/src/soc/rockchip/rk3288/software_i2c.c +++ b/src/soc/rockchip/rk3288/software_i2c.c @@ -73,8 +73,8 @@ void software_i2c_attach(unsigned int bus) /* Mux pins to GPIO function for software I2C emulation. */ switch (bus) { case 0: - clrbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - clrbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + clrbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + clrbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_GPIO(IOMUX_I2C1)); @@ -108,8 +108,8 @@ void software_i2c_detach(unsigned int bus) /* Mux pins back to hardware I2C controller. */ switch (bus) { case 0: - setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); - setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + setbits32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); break; case 1: write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 3223a4ddd4..e0649754b4 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -81,9 +81,9 @@ void tsadc_init(void) { rkclk_configure_tsadc(TSADC_CLOCK_HZ); - setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT); + setbits32(&rk3288_tsadc->auto_con, LAST_TSHUT); - setbits_le32(&rk3288_tsadc->int_en, + setbits32(&rk3288_tsadc->int_en, TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 | TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1); @@ -96,7 +96,7 @@ void tsadc_init(void) write32(&rk3288_tsadc->comp2_shut, TSADC_SHUT_VALUE); /* polarity set to high,channel1 for cpu,channel2 for gpu */ - setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | + setbits32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN | SRC1_EN | AUTO_EN); /* @@ -104,5 +104,5 @@ void tsadc_init(void) since the tshut polarity defalut low active, so if you enable tsadc iomux,it will output high */ - setbits_le32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); + setbits32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT); } diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 5252232f39..f9c49c33d7 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -374,9 +374,9 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) write32(&cru_ptr->dpll_con[3], RK_CLRSETBITS(PLL_DSMPD_MASK << PLL_DSMPD_SHIFT, PLL_FRAC_MODE << PLL_DSMPD_SHIFT)); - clrsetbits_le32(&cru_ptr->dpll_con[2], - PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, - 0 << PLL_FRACDIV_SHIFT); + clrsetbits32(&cru_ptr->dpll_con[2], + PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT, + 0 << PLL_FRACDIV_SHIFT); /* * Configure SSC divval. diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 3c6cbe648f..358bb6a7e0 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -60,15 +60,15 @@ u32 get_saradc_value(u32 chn) rkclk_configure_saradc(SARADC_HZ); /* power down adc converter */ - clrbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + clrbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); /* select channel */ - clrsetbits_le32(&rk3399_saradc->ctrl, - ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, - chn << ADC_CHN_SEL_SHIFT); + clrsetbits32(&rk3399_saradc->ctrl, + ADC_CHN_SEL_MASK << ADC_CHN_SEL_SHIFT, + chn << ADC_CHN_SEL_SHIFT); /* power up */ - setbits_le32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); + setbits32(&rk3399_saradc->ctrl, ADC_PWR_CTRL); udelay(SARADC_DELAY_PU); diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 0e8cda60d7..3fe22f2502 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -120,26 +120,26 @@ static void phy_dll_bypass_set(u32 channel, if (freq <= 125*MHz) { /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - setbits_le32(&denali_phy[86], (0x3 << 2) << 8); - setbits_le32(&denali_phy[214], (0x3 << 2) << 8); - setbits_le32(&denali_phy[342], (0x3 << 2) << 8); - setbits_le32(&denali_phy[470], (0x3 << 2) << 8); + setbits32(&denali_phy[86], (0x3 << 2) << 8); + setbits32(&denali_phy[214], (0x3 << 2) << 8); + setbits32(&denali_phy[342], (0x3 << 2) << 8); + setbits32(&denali_phy[470], (0x3 << 2) << 8); /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - setbits_le32(&denali_phy[547], (0x3 << 2) << 16); - setbits_le32(&denali_phy[675], (0x3 << 2) << 16); - setbits_le32(&denali_phy[803], (0x3 << 2) << 16); + setbits32(&denali_phy[547], (0x3 << 2) << 16); + setbits32(&denali_phy[675], (0x3 << 2) << 16); + setbits32(&denali_phy[803], (0x3 << 2) << 16); } else { /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); + clrbits32(&denali_phy[86], (0x3 << 2) << 8); + clrbits32(&denali_phy[214], (0x3 << 2) << 8); + clrbits32(&denali_phy[342], (0x3 << 2) << 8); + clrbits32(&denali_phy[470], (0x3 << 2) << 8); /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); + clrbits32(&denali_phy[547], (0x3 << 2) << 16); + clrbits32(&denali_phy[675], (0x3 << 2) << 16); + clrbits32(&denali_phy[803], (0x3 << 2) << 16); } } @@ -164,23 +164,23 @@ static void set_memory_map(u32 channel, cs_map = (sdram_ch->rank > 1) ? 3 : 1; reduc = (sdram_ch->bw == 2) ? 0 : 1; - clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); - clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); + clrsetbits32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); + clrsetbits32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); - clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), - cs_map | (reduc << 16)); + clrsetbits32(&denali_ctl[196], 0x3 | (1 << 16), + cs_map | (reduc << 16)); /* PI_199 PI_COL_DIFF:RW:0:4 */ - clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); + clrsetbits32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ - clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); + clrsetbits32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), + ((3 - sdram_ch->bk) << 16) | + ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ - clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); + clrsetbits32(&denali_pi[41], 0xf << 24, cs_map << 24); if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3)) write32(&denali_pi[34], 0x2EC7FFFF); } @@ -244,84 +244,84 @@ static void set_ds_odt(u32 channel, reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); - clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); + clrsetbits32(&denali_phy[6], 0xffffff, reg_value); + clrsetbits32(&denali_phy[134], 0xffffff, reg_value); + clrsetbits32(&denali_phy[262], 0xffffff, reg_value); + clrsetbits32(&denali_phy[390], 0xffffff, reg_value); /* * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 * sets termination values for read/idle cycles and drive strength * for write cycles for DQS */ - clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); + clrsetbits32(&denali_phy[7], 0xffffff, reg_value); + clrsetbits32(&denali_phy[135], 0xffffff, reg_value); + clrsetbits32(&denali_phy[263], 0xffffff, reg_value); + clrsetbits32(&denali_phy[391], 0xffffff, reg_value); /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); + clrsetbits32(&denali_phy[544], 0xff, reg_value); + clrsetbits32(&denali_phy[672], 0xff, reg_value); + clrsetbits32(&denali_phy[800], 0xff, reg_value); /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ - clrsetbits_le32(&denali_phy[928], 0xff, reg_value); + clrsetbits32(&denali_phy[928], 0xff, reg_value); /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ - clrsetbits_le32(&denali_phy[937], 0xff, reg_value); + clrsetbits32(&denali_phy[937], 0xff, reg_value); /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ - clrsetbits_le32(&denali_phy[935], 0xff, reg_value); + clrsetbits32(&denali_phy[935], 0xff, reg_value); /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); + clrsetbits32(&denali_phy[939], 0xff, reg_value); /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); + clrsetbits32(&denali_phy[929], 0xff, reg_value); /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ - clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_n | (tsel_wr_select_p << 4)); - clrsetbits_le32(&denali_phy[925], 0xff, - tsel_rd_select_n | (tsel_rd_select_p << 4)); + clrsetbits32(&denali_phy[924], 0xff, + tsel_wr_select_n | (tsel_wr_select_p << 4)); + clrsetbits32(&denali_phy[925], 0xff, + tsel_rd_select_n | (tsel_rd_select_p << 4)); /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 16; - clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[5], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[133], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[261], 0x7 << 16, reg_value); + clrsetbits32(&denali_phy[389], 0x7 << 16, reg_value); /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[6], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[134], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[262], 0x7 << 24, reg_value); + clrsetbits32(&denali_phy[390], 0x7 << 24, reg_value); /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ reg_value = tsel_wr_en << 8; - clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[518], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[646], 0x1 << 8, reg_value); + clrsetbits32(&denali_phy[774], 0x1 << 8, reg_value); /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ reg_value = tsel_wr_en << 17; - clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[933], 0x1 << 17, reg_value); /* * pad_rst/cke/cs/clk_term tsel 1bits * DENALI_PHY_938/936/940/934 offset_17 */ - clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[938], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[936], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[940], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[934], 0x1 << 17, reg_value); /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ - clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); + clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value); } static void phy_io_config(u32 channel, @@ -410,18 +410,18 @@ static void phy_io_config(u32 channel, reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ - clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); + clrsetbits32(&denali_phy[913], 0xfff << 8, reg_value << 8); /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ - clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); + clrsetbits32(&denali_phy[914], 0xfff, reg_value); /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ - clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); + clrsetbits32(&denali_phy[914], 0xfff << 16, reg_value << 16); /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ - clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); + clrsetbits32(&denali_phy[915], 0xfff, reg_value); reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ - clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); + clrsetbits32(&denali_phy[915], 0xfff << 16, reg_value << 16); if (sdram_params->dramtype == LPDDR4) mode_sel = 0x6; @@ -431,21 +431,21 @@ static void phy_io_config(u32 channel, mode_sel = 0x1; /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); + clrsetbits32(&denali_phy[924], 0x7 << 15, mode_sel << 15); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); + clrsetbits32(&denali_phy[926], 0x7 << 6, mode_sel << 6); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); + clrsetbits32(&denali_phy[927], 0x7 << 6, mode_sel << 6); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[928], 0x7 << 14, mode_sel << 14); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[929], 0x7 << 14, mode_sel << 14); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[935], 0x7 << 14, mode_sel << 14); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[937], 0x7 << 14, mode_sel << 14); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); + clrsetbits32(&denali_phy[939], 0x7 << 14, mode_sel << 14); /* speed setting */ @@ -459,21 +459,21 @@ static void phy_io_config(u32 channel, speed = 0x3; /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); + clrsetbits32(&denali_phy[924], 0x3 << 21, speed << 21); /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); + clrsetbits32(&denali_phy[926], 0x3 << 9, speed << 9); /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); + clrsetbits32(&denali_phy[927], 0x3 << 9, speed << 9); /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[928], 0x3 << 17, speed << 17); /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[929], 0x3 << 17, speed << 17); /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[935], 0x3 << 17, speed << 17); /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[937], 0x3 << 17, speed << 17); /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); + clrsetbits32(&denali_phy[939], 0x3 << 17, speed << 17); } static int pctl_cfg(u32 channel, @@ -505,13 +505,13 @@ static int pctl_cfg(u32 channel, write32(&denali_phy[912], sdram_params->phy_regs.denali_phy[912]); pwrup_srefresh_exit = read32(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; - clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); + clrbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); + clrsetbits32(&denali_phy[957], 0x3 << 24, 1 << 24); - setbits_le32(&denali_pi[0], START); - setbits_le32(&denali_ctl[0], START); + setbits32(&denali_pi[0], START); + setbits32(&denali_ctl[0], START); while (1) { tmp = read32(&denali_phy[920]); @@ -539,31 +539,31 @@ static int pctl_cfg(u32 channel, * dqs_tsel_wr_end[7:4] add Half cycle */ tmp = (read32(&denali_phy[84]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[212]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[340]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); tmp = (read32(&denali_phy[468]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); + clrsetbits32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); /* * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 * dq_tsel_wr_end[7:4] add Half cycle */ tmp = (read32(&denali_phy[83]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[211]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[339]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); tmp = (read32(&denali_phy[467]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); + clrsetbits32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); phy_io_config(channel, sdram_params); /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); + clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24); /* FIXME: need to care ERROR bit */ stopwatch_init_msecs_expire(&sw, 100); @@ -572,8 +572,8 @@ static int pctl_cfg(u32 channel, return -1; } - clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit); + clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, + pwrup_srefresh_exit); return 0; } @@ -587,10 +587,10 @@ static void select_per_cs_training_index(u32 channel, u32 rank) * PHY_8/136/264/392 * phy_per_cs_training_index_X 1bit offset_24 */ - clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[8], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[136], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[264], 0x1 << 24, rank << 24); + clrsetbits32(&denali_phy[392], 0x1 << 24, rank << 24); } } @@ -601,26 +601,26 @@ static void override_write_leveling_value(u32 channel) u32 byte; /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - setbits_le32(&denali_phy[896], 1); + setbits32(&denali_phy[896], 1); /* * PHY_8/136/264/392 * phy_per_cs_training_multicast_en_X 1bit offset_16 */ - clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[8], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[136], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[264], 0x1 << 16, 1 << 16); + clrsetbits32(&denali_phy[392], 0x1 << 16, 1 << 16); for (byte = 0; byte < 4; byte++) - clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, + clrsetbits32(&denali_phy[63 + (128 * byte)], 0xffff << 16, 0x200 << 16); /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - clrbits_le32(&denali_phy[896], 1); + clrbits32(&denali_phy[896], 1); /* CTL_200 ctrlupd_req 1bit offset_8 */ - clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); + clrsetbits32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); } static int data_training(u32 channel, @@ -635,7 +635,7 @@ static int data_training(u32 channel, u32 reg_value = 0; /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - setbits_le32(&denali_phy[927], (1 << 22)); + setbits32(&denali_phy[927], (1 << 22)); if (training_flag == PI_FULL_TRAINING) { if (sdram_params->dramtype == LPDDR4) { @@ -657,11 +657,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_100 PI_CALVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); + clrsetbits32(&denali_pi[100], 0x3 << 8, 0x2 << 8); /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[92], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); + clrsetbits32(&denali_pi[92], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -690,7 +690,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[100], 0x3 << 8); + clrbits32(&denali_pi[100], 0x3 << 8); } /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ @@ -698,11 +698,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_60 PI_WRLVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); + clrsetbits32(&denali_pi[60], 0x3 << 8, 0x2 << 8); /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[59], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); + clrsetbits32(&denali_pi[59], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -736,7 +736,7 @@ static int data_training(u32 channel, } override_write_leveling_value(channel); - clrbits_le32(&denali_pi[60], 0x3 << 8); + clrbits32(&denali_pi[60], 0x3 << 8); } /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ @@ -758,22 +758,22 @@ static int data_training(u32 channel, * phy_dqs_tsel_enable_X 3bits * DENALI_PHY_6/134/262/390 offset_24 */ - clrbits_le32(&denali_phy[6], 0x7 << 24); - clrbits_le32(&denali_phy[134], 0x7 << 24); - clrbits_le32(&denali_phy[262], 0x7 << 24); - clrbits_le32(&denali_phy[390], 0x7 << 24); + clrbits32(&denali_phy[6], 0x7 << 24); + clrbits32(&denali_phy[134], 0x7 << 24); + clrbits32(&denali_phy[262], 0x7 << 24); + clrbits32(&denali_phy[390], 0x7 << 24); } for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); + clrsetbits32(&denali_pi[80], 0x3 << 24, 0x2 << 24); /* * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 * PI_RDLVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); + clrsetbits32(&denali_pi[74], + (0x1 << 16) | (0x3 << 24), + (0x1 << 16) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -805,7 +805,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[80], 0x3 << 24); + clrbits32(&denali_pi[80], 0x3 << 24); if (sdram_params->dramtype != LPDDR4) { /* @@ -813,10 +813,10 @@ static int data_training(u32 channel, * DENALI_PHY_6/134/262/390 offset_24 */ tmp = reg_value << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, tmp); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[6], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[134], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[262], 0x7 << 24, tmp); + clrsetbits32(&denali_phy[390], 0x7 << 24, tmp); } } @@ -825,11 +825,11 @@ static int data_training(u32 channel, for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); + clrsetbits32(&denali_pi[80], 0x3 << 16, 0x2 << 16); /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 8) | (0x3 << 24), - (0x1 << 8) | (i << 24)); + clrsetbits32(&denali_pi[74], + (0x1 << 8) | (0x3 << 24), + (0x1 << 8) | (i << 24)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -850,7 +850,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[80], 0x3 << 16); + clrbits32(&denali_pi[80], 0x3 << 16); } /* wdq leveling(LPDDR4 support) */ @@ -861,13 +861,13 @@ static int data_training(u32 channel, * disable PI_WDQLVL_VREF_EN before wdq leveling? * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */ - clrbits_le32(&denali_pi[181], 0x1 << 8); + clrbits32(&denali_pi[181], 0x1 << 8); /* PI_124 PI_WDQLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); + clrsetbits32(&denali_pi[124], 0x3 << 16, 0x2 << 16); /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[121], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); + clrsetbits32(&denali_pi[121], + (0x1 << 8) | (0x3 << 16), + (0x1 << 8) | (i << 16)); while (1) { /* PI_174 PI_INT_STATUS:RD:8:18 */ @@ -882,11 +882,11 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } - clrbits_le32(&denali_pi[124], 0x3 << 16); + clrbits32(&denali_pi[124], 0x3 << 16); } /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - clrbits_le32(&denali_phy[927], (1 << 22)); + clrbits32(&denali_phy[927], (1 << 22)); return 0; } @@ -960,8 +960,8 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ if (sdram_params->ch[channel].rank == 1) - setbits_le32(&rk3399_ddr_pctl[channel]->denali_ctl[276], - 1 << 17); + setbits32(&rk3399_ddr_pctl[channel]->denali_ctl[276], + 1 << 17); } write32(&rk3399_pmugrf->os_reg2, sys_reg); @@ -971,7 +971,7 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) write32(&pmucru_ptr->pmucru_rstnhold_con[1], PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | PRESET_GPIO1_HOLD(1)); - clrsetbits_le32(&cru_ptr->glb_rst_con, 0x3, 0x3); + clrsetbits32(&cru_ptr->glb_rst_con, 0x3, 0x3); } static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) @@ -1005,7 +1005,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) for (channel = 0; channel < ch_count; channel++) { denali_phy = rk3399_ddr_publ[channel]->denali_phy; - clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); + clrsetbits32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { printk(BIOS_ERR, "index1 training failed, reset\n"); board_reset(); diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 7ec24648a2..78ce1e366e 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -100,7 +100,7 @@ void tsadc_init(uint32_t polarity) rkclk_configure_tsadc(TSADC_CLOCK_HZ); /* tsadc power sequence */ - clrbits_le32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); + clrbits32(&rk3399_tsadc->user_con, ADC_POWER_CTRL); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_ON); udelay(50); write32(&rk3399_grf->tsadc_testbit_l, GRF_TSADC_TSEN_PD0_OFF); @@ -125,9 +125,9 @@ void tsadc_init(uint32_t polarity) write32(&rk3399_tsadc->auto_period_ht, AUTO_PERIOD_HT); write32(&rk3399_tsadc->hight_tshut_debounce, AUTO_DEBOUNCE_HT); /* Enable the src0, negative temprature coefficient */ - setbits_le32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); + setbits32(&rk3399_tsadc->auto_con, Q_SEL | SRC0_EN); udelay(100); - setbits_le32(&rk3399_tsadc->auto_con, AUTO_EN); + setbits32(&rk3399_tsadc->auto_con, AUTO_EN); write32(&rk3399_tsadc->comp0_shut, TSADC_SHUT_VALUE); write32(&rk3399_tsadc->int_en, TSHUT_CRU_EN_SRC0 | TSHUT_GPIO_EN_SRC0); diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index e016fbf7c1..434a99ef11 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -54,8 +54,8 @@ static void tcphy_cfg_24m(struct rk3399_tcphy *tcphy) write32(&tcphy->lane[i].tx_rcvdet_st_tmr, 0x30); } - clrsetbits_le32(&tcphy->cmn_diag_hsclk_sel, - TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG); + clrsetbits32(&tcphy->cmn_diag_hsclk_sel, + TCPHY_CMN_HSCLK_PLL_MASK, TCPHY_CMN_HSCLK_PLL_CONFIG); } static void tcphy_phy_init(struct rk3399_tcphy *tcphy) @@ -78,11 +78,11 @@ static void tcphy_phy_init(struct rk3399_tcphy *tcphy) static void reset_dwc3(struct rockchip_usb_dwc3 *dwc3) { /* Before Resetting PHY, put Core in Reset */ - setbits_le32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET); + setbits32(&dwc3->ctl, DWC3_GCTL_CORESOFTRESET); /* Assert USB3 PHY reset */ - setbits_le32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); + setbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); /* Assert USB2 PHY reset */ - setbits_le32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); + setbits32(&dwc3->usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST); } static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) @@ -94,7 +94,7 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3) assert(ctl & DWC3_GCTL_CORESOFTRESET); /* Clear USB3 PHY reset (oddly enough, this is really necessary). */ - clrbits_le32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); + clrbits32(&dwc3->usb3pipectl, DWC3_GUSB3PIPECTL_PHYSOFTRST); /* Clear USB2 PHY and core reset. */ usb2phycfg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index efb0de31f3..e762af1908 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -425,7 +425,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) @@ -460,7 +460,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } /** @@ -644,7 +644,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { - clrsetbits_le32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK, + clrsetbits32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); } @@ -664,7 +664,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); return -1; } - clrsetbits_le32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK, + clrsetbits32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK, (div & AUDIO_1_RATIO_MASK)); return 0; } diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index fa19eb1763..ca3dbd9921 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -28,27 +28,27 @@ void system_clock_init(struct mem_timings *mem, /* Turn on the MCT as early as possible. */ exynos_mct->g_tcon |= (1 << 8); - clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); + clrbits32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cpu); } while ((val | MUX_APLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); + clrbits32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); - clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK); + clrbits32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { val = read32(&exynos_clock->mux_stat_top2); } while ((val | tmp) != val); - clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); + clrbits32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK); do { val = read32(&exynos_clock->mux_stat_cdrex); } while ((val | MUX_BPLL_SEL_MASK) != val); @@ -94,7 +94,7 @@ void system_clock_init(struct mem_timings *mem, } while (0 != val); /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + clrbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set APLL */ write32(&exynos_clock->apll_con1, APLL_CON1_VAL); @@ -105,7 +105,7 @@ void system_clock_init(struct mem_timings *mem, ; /* now it is safe to switch to APLL */ - setbits_le32(&exynos_clock->src_cpu, APLL_FOUT); + setbits32(&exynos_clock->src_cpu, APLL_FOUT); /* Set MPLL */ write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); @@ -118,7 +118,7 @@ void system_clock_init(struct mem_timings *mem, * Configure MUX_MPLL_FOUT to choose the direct clock source * path and avoid the fixed DIV/2 block to save power */ - setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL); /* Set BPLL */ if (mem->use_bpll) { @@ -128,7 +128,7 @@ void system_clock_init(struct mem_timings *mem, while ((read32(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; - setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); + setbits32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL); } /* Set CPLL */ @@ -280,124 +280,124 @@ void system_clock_init(struct mem_timings *mem, void clock_gate(void) { /* CLK_GATE_IP_SYSRGT */ - clrbits_le32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); + clrbits32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK); /* CLK_GATE_IP_ACP */ - clrbits_le32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | - CLK_SMMUSSS_MASK | - CLK_SMMUMDMA_MASK | - CLK_ID_REMAPPER_MASK | - CLK_G2D_MASK | - CLK_SSS_MASK | - CLK_MDMA_MASK | - CLK_SECJTAG_MASK); + clrbits32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK | + CLK_SMMUSSS_MASK | + CLK_SMMUMDMA_MASK | + CLK_ID_REMAPPER_MASK | + CLK_G2D_MASK | + CLK_SSS_MASK | + CLK_MDMA_MASK | + CLK_SECJTAG_MASK); /* CLK_GATE_BUS_SYSLFT */ - clrbits_le32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); + clrbits32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK); /* CLK_GATE_IP_ISP0 */ - clrbits_le32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | - CLK_WDT_ISP_MASK | - CLK_PWM_ISP_MASK | - CLK_MTCADC_ISP_MASK | - CLK_I2C1_ISP_MASK | - CLK_I2C0_ISP_MASK | - CLK_MPWM_ISP_MASK | - CLK_MCUCTL_ISP_MASK | - CLK_INT_COMB_ISP_MASK | - CLK_SMMU_MCUISP_MASK | - CLK_SMMU_SCALERP_MASK | - CLK_SMMU_SCALERC_MASK | - CLK_SMMU_FD_MASK | - CLK_SMMU_DRC_MASK | - CLK_SMMU_ISP_MASK | - CLK_GICISP_MASK | - CLK_ARM9S_MASK | - CLK_MCUISP_MASK | - CLK_SCALERP_MASK | - CLK_SCALERC_MASK | - CLK_FD_MASK | - CLK_DRC_MASK | - CLK_ISP_MASK); + clrbits32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK | + CLK_WDT_ISP_MASK | + CLK_PWM_ISP_MASK | + CLK_MTCADC_ISP_MASK | + CLK_I2C1_ISP_MASK | + CLK_I2C0_ISP_MASK | + CLK_MPWM_ISP_MASK | + CLK_MCUCTL_ISP_MASK | + CLK_INT_COMB_ISP_MASK | + CLK_SMMU_MCUISP_MASK | + CLK_SMMU_SCALERP_MASK | + CLK_SMMU_SCALERC_MASK | + CLK_SMMU_FD_MASK | + CLK_SMMU_DRC_MASK | + CLK_SMMU_ISP_MASK | + CLK_GICISP_MASK | + CLK_ARM9S_MASK | + CLK_MCUISP_MASK | + CLK_SCALERP_MASK | + CLK_SCALERC_MASK | + CLK_FD_MASK | + CLK_DRC_MASK | + CLK_ISP_MASK); /* CLK_GATE_IP_ISP1 */ - clrbits_le32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | - CLK_SPI0_ISP_MASK | - CLK_SMMU3DNR_MASK | - CLK_SMMUDIS1_MASK | - CLK_SMMUDIS0_MASK | - CLK_SMMUODC_MASK | - CLK_3DNR_MASK | - CLK_DIS_MASK | - CLK_ODC_MASK); + clrbits32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK | + CLK_SPI0_ISP_MASK | + CLK_SMMU3DNR_MASK | + CLK_SMMUDIS1_MASK | + CLK_SMMUDIS0_MASK | + CLK_SMMUODC_MASK | + CLK_3DNR_MASK | + CLK_DIS_MASK | + CLK_ODC_MASK); /* CLK_GATE_SCLK_ISP */ - clrbits_le32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); + clrbits32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK); /* CLK_GATE_IP_GSCL */ - clrbits_le32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | - CLK_SMMUFIMC_LITE1_MASK | - CLK_SMMUFIMC_LITE0_MASK | - CLK_SMMUGSCL3_MASK | - CLK_SMMUGSCL2_MASK | - CLK_SMMUGSCL1_MASK | - CLK_SMMUGSCL0_MASK | - CLK_GSCL_WRAP_B_MASK | - CLK_GSCL_WRAP_A_MASK | - CLK_CAMIF_TOP_MASK | - CLK_GSCL3_MASK | - CLK_GSCL2_MASK | - CLK_GSCL1_MASK | - CLK_GSCL0_MASK); + clrbits32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | + CLK_SMMUFIMC_LITE1_MASK | + CLK_SMMUFIMC_LITE0_MASK | + CLK_SMMUGSCL3_MASK | + CLK_SMMUGSCL2_MASK | + CLK_SMMUGSCL1_MASK | + CLK_SMMUGSCL0_MASK | + CLK_GSCL_WRAP_B_MASK | + CLK_GSCL_WRAP_A_MASK | + CLK_CAMIF_TOP_MASK | + CLK_GSCL3_MASK | + CLK_GSCL2_MASK | + CLK_GSCL1_MASK | + CLK_GSCL0_MASK); /* CLK_GATE_IP_DISP1 */ - clrbits_le32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | - CLK_ASYNCTVX_MASK | - CLK_HDMI_MASK | - CLK_MIXER_MASK | - CLK_DSIM1_MASK); + clrbits32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK | + CLK_ASYNCTVX_MASK | + CLK_HDMI_MASK | + CLK_MIXER_MASK | + CLK_DSIM1_MASK); /* CLK_GATE_IP_MFC */ - clrbits_le32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | - CLK_SMMUMFCL_MASK | - CLK_MFC_MASK); + clrbits32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK | + CLK_SMMUMFCL_MASK | + CLK_MFC_MASK); /* CLK_GATE_IP_GEN */ - clrbits_le32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | - CLK_SMMUJPEG_MASK | - CLK_SMMUROTATOR_MASK | - CLK_MDMA1_MASK | - CLK_JPEG_MASK | - CLK_ROTATOR_MASK); + clrbits32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK | + CLK_SMMUJPEG_MASK | + CLK_SMMUROTATOR_MASK | + CLK_MDMA1_MASK | + CLK_JPEG_MASK | + CLK_ROTATOR_MASK); /* CLK_GATE_IP_FSYS */ - clrbits_le32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | - CLK_SMMUMCU_IOP_MASK | - CLK_SATA_PHY_I2C_MASK | - CLK_SATA_PHY_CTRL_MASK | - CLK_MCUCTL_MASK | - CLK_NFCON_MASK | - CLK_SMMURTIC_MASK | - CLK_RTIC_MASK | - CLK_MIPI_HSI_MASK | - CLK_USBOTG_MASK | - CLK_SATA_MASK | - CLK_PDMA1_MASK | - CLK_PDMA0_MASK | - CLK_MCU_IOP_MASK); + clrbits32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK | + CLK_SMMUMCU_IOP_MASK | + CLK_SATA_PHY_I2C_MASK | + CLK_SATA_PHY_CTRL_MASK | + CLK_MCUCTL_MASK | + CLK_NFCON_MASK | + CLK_SMMURTIC_MASK | + CLK_RTIC_MASK | + CLK_MIPI_HSI_MASK | + CLK_USBOTG_MASK | + CLK_SATA_MASK | + CLK_PDMA1_MASK | + CLK_PDMA0_MASK | + CLK_MCU_IOP_MASK); /* CLK_GATE_IP_PERIC */ - clrbits_le32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | - CLK_HS_I2C2_MASK | - CLK_HS_I2C1_MASK | - CLK_HS_I2C0_MASK | - CLK_AC97_MASK | - CLK_SPDIF_MASK | - CLK_PCM2_MASK | - CLK_PCM1_MASK | - CLK_I2S2_MASK | - CLK_SPI2_MASK | - CLK_SPI0_MASK); + clrbits32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK | + CLK_HS_I2C2_MASK | + CLK_HS_I2C1_MASK | + CLK_HS_I2C0_MASK | + CLK_AC97_MASK | + CLK_SPDIF_MASK | + CLK_PCM2_MASK | + CLK_PCM1_MASK | + CLK_I2S2_MASK | + CLK_SPI2_MASK | + CLK_SPI0_MASK); /* * CLK_GATE_IP_PERIS @@ -405,33 +405,33 @@ void clock_gate(void) * register (PRO_ID) works correctly when the OS kernel determines * which chip it is running on. */ - clrbits_le32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | - CLK_TZPC9_MASK | - CLK_TZPC8_MASK | - CLK_TZPC7_MASK | - CLK_TZPC6_MASK | - CLK_TZPC5_MASK | - CLK_TZPC4_MASK | - CLK_TZPC3_MASK | - CLK_TZPC2_MASK | - CLK_TZPC1_MASK | - CLK_TZPC0_MASK); + clrbits32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK | + CLK_TZPC9_MASK | + CLK_TZPC8_MASK | + CLK_TZPC7_MASK | + CLK_TZPC6_MASK | + CLK_TZPC5_MASK | + CLK_TZPC4_MASK | + CLK_TZPC3_MASK | + CLK_TZPC2_MASK | + CLK_TZPC1_MASK | + CLK_TZPC0_MASK); /* CLK_GATE_BLOCK */ - clrbits_le32(&exynos_clock->gate_block, CLK_ACP_MASK); + clrbits32(&exynos_clock->gate_block, CLK_ACP_MASK); /* CLK_GATE_IP_CDREX */ - clrbits_le32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | - CLK_DPHY1_MASK | - CLK_TZASC_DRBXR_MASK); + clrbits32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK | + CLK_DPHY1_MASK | + CLK_TZASC_DRBXR_MASK); } void clock_init_dp_clock(void) { /* DP clock enable */ - setbits_le32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); + setbits32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW); /* We run DP at 267 Mhz */ - setbits_le32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); + setbits32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } diff --git a/src/soc/samsung/exynos5250/dp-reg.c b/src/soc/samsung/exynos5250/dp-reg.c index e57b0af2f9..fa5e11cf2a 100644 --- a/src/soc/samsung/exynos5250/dp-reg.c +++ b/src/soc/samsung/exynos5250/dp-reg.c @@ -34,8 +34,8 @@ void s5p_dp_reset(struct s5p_dp_device *dp) write32(&base->dp_tx_sw_reset, RESET_DP_TX); /* Stop Video */ - clrbits_le32(&base->video_ctl_1, VIDEO_EN); - clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + clrbits32(&base->video_ctl_1, VIDEO_EN); + clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE); reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | @@ -124,12 +124,12 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) reg = PLL_LOCK_CHG; write32(&base->common_int_sta_1, reg); - clrbits_le32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); + clrbits32(&base->dp_debug_ctl, (F_PLL_LOCK | PLL_LOCK_CTRL)); /* Power up PLL */ if (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { - clrbits_le32(&base->dp_pll_ctl, DP_PLL_PD); + clrbits32(&base->dp_pll_ctl, DP_PLL_PD); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -143,7 +143,7 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp) } /* Enable Serdes FIFO function and Link symbol clock domain module */ - clrbits_le32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | + clrbits32(&base->func_en_2, (SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N)); return 0; } @@ -158,7 +158,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) write32(&base->dp_int_sta, reg); /* Disable AUX channel module */ - setbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + setbits32(&base->func_en_2, AUX_FUNC_EN_N); /* Disable AUX transaction H/W retry */ reg = (3 & AUX_BIT_PERIOD_MASK) << AUX_BIT_PERIOD_SHIFT; @@ -172,7 +172,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp) write32(&base->aux_ch_defer_dtl, reg); /* Enable AUX channel module */ - clrbits_le32(&base->func_en_2, AUX_FUNC_EN_N); + clrbits32(&base->func_en_2, AUX_FUNC_EN_N); } int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) @@ -181,7 +181,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) struct exynos5_dp *base = dp->base; /* Enable AUX CH operation */ - setbits_le32(&base->aux_ch_ctl_2, AUX_EN); + setbits32(&base->aux_ch_ctl_2, AUX_EN); /* Is AUX CH command reply received? */ reg = read32(&base->dp_int_sta); @@ -386,7 +386,7 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, struct exynos5_dp *base = dp->base; if (type == REGISTER_M) { - setbits_le32(&base->sys_ctl_4, FIX_M_VID); + setbits32(&base->sys_ctl_4, FIX_M_VID); reg = m_value >> M_VID_0_VALUE_SHIFT; write32(&base->m_vid_0, reg); @@ -406,7 +406,7 @@ void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp, reg = (n_value >> N_VID_2_VALUE_SHIFT); write32(&base->n_vid_2, reg); } else { - clrbits_le32(&base->sys_ctl_4, FIX_M_VID); + clrbits32(&base->sys_ctl_4, FIX_M_VID); write32(&base->n_vid_0, 0x00); write32(&base->n_vid_1, 0x80); diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 64980a1aec..2e8acf2688 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -100,7 +100,7 @@ short console_row; /* Bypass FIMD of DISP1_BLK */ static void fimd_bypass(void) { - setbits_le32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); + setbits32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1); exynos_sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1; } @@ -145,7 +145,7 @@ void fb_init(unsigned long int fb_size, void *lcdbase, write32(&exynos_fimd->vidosd0b, val); write32(&exynos_fimd->vidosd0c, pd->xres * pd->yres); - setbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); + setbits32(&exynos_fimd->shadowcon, CHANNEL0_EN); val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; @@ -159,7 +159,7 @@ void fb_init(unsigned long int fb_size, void *lcdbase, void exynos_fimd_disable(void) { write32(&exynos_fimd->wincon0, 0); - clrbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN); + clrbits32(&exynos_fimd->shadowcon, CHANNEL0_EN); } #endif @@ -205,16 +205,16 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, /* Set to use the register calculated M/N video */ s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); - clrbits_le32(&base->video_ctl_10, FORMAT_SEL); + clrbits32(&base->video_ctl_10, FORMAT_SEL); /* Disable video mute */ - clrbits_le32(&base->video_ctl_1, HDCP_VIDEO_MUTE); + clrbits32(&base->video_ctl_1, HDCP_VIDEO_MUTE); /* Configure video slave mode */ s5p_dp_enable_video_master(dp); /* Enable video */ - setbits_le32(&base->video_ctl_1, VIDEO_EN); + setbits32(&base->video_ctl_1, VIDEO_EN); timeout = s5p_dp_is_video_stream_on(dp); if (timeout) { @@ -258,7 +258,7 @@ static int s5p_dp_enable_scramble(struct s5p_dp_device *dp) u8 data; struct exynos5_dp *base = dp->base; - clrbits_le32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); + clrbits32(&base->dp_training_ptn_set, SCRAMBLING_DISABLE); if (s5p_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, &data)) { @@ -288,7 +288,7 @@ static int s5p_dp_init_dp(struct s5p_dp_device *dp) s5p_dp_reset(dp); /* SW defined function Normal operation */ - clrbits_le32(&base->func_en_1, SW_FUNC_EN_N); + clrbits32(&base->func_en_1, SW_FUNC_EN_N); ret = s5p_dp_init_analog_func(dp); if (!ret) @@ -397,7 +397,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, struct exynos5_dp *base = dp->base; /* Stop Video */ - clrbits_le32(&base->video_ctl_1, VIDEO_EN); + clrbits32(&base->video_ctl_1, VIDEO_EN); stopwatch_init_msecs_expire(&sw, PLL_LOCK_TIMEOUT); @@ -411,12 +411,12 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, printk(BIOS_SPEW, "PLL is %slocked\n", pll_is_locked == PLL_LOCKED ? "": "not "); /* Reset Macro */ - setbits_le32(&base->dp_phy_test, MACRO_RST); + setbits32(&base->dp_phy_test, MACRO_RST); /* 10 us is the minimum reset time. */ udelay(10); - clrbits_le32(&base->dp_phy_test, MACRO_RST); + clrbits32(&base->dp_phy_test, MACRO_RST); /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < max_lane; lane++) @@ -534,7 +534,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device) base = dp->base; /* Enable enhanced mode */ - setbits_le32(&base->sys_ctl_4, ENHANCED); + setbits32(&base->sys_ctl_4, ENHANCED); write32(&base->lane_count_set, dp->link_train.lane_count); write32(&base->link_bw_set, dp->link_train.link_rate); diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index e649e949c8..37369b3482 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -26,7 +26,7 @@ static void ps_hold_setup(void) { /* Set PS-Hold high */ - setbits_le32(&exynos_power->ps_hold_ctrl, + setbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); } @@ -35,7 +35,7 @@ void power_reset(void) /* Clear inform1 so there's no change we think we've got a wake reset */ exynos_power->inform1 = 0; - setbits_le32(&exynos_power->sw_reset, 1); + setbits32(&exynos_power->sw_reset, 1); } void do_board_reset(void) @@ -46,7 +46,7 @@ void do_board_reset(void) /* This function never returns */ void power_shutdown(void) { - clrbits_le32(&exynos_power->ps_hold_ctrl, + clrbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); halt(); @@ -54,13 +54,13 @@ void power_shutdown(void) void power_enable_dp_phy(void) { - setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); + setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); } void power_enable_hw_thermal_trip(void) { /* Enable HW thermal trip */ - setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); + setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); } uint32_t power_read_reset_status(void) @@ -84,7 +84,7 @@ int power_init(void) void power_enable_xclkout(void) { /* use xxti for xclk out */ - clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, PMU_DEBUG_XXTI); } diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index e35f888177..4d5e01f493 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -42,8 +42,8 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, ASSERT(todo % 4 == 0); out_bytes = in_bytes = todo; - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); write32(®s->pkt_cnt, ((todo * 8) / 32) | SPI_PACKET_CNT_EN); while (in_bytes) { @@ -81,22 +81,22 @@ int exynos_spi_open(struct exynos_spi *regs) /* set FB_CLK_SEL */ write32(®s->fb_clk, SPI_FB_DELAY_180); /* set CH_WIDTH and BUS_WIDTH as word */ - setbits_le32(®s->mode_cfg, + setbits32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); - clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ /* clear rx and tx channel if set previously */ - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->swap_cfg, - SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); + setbits32(®s->swap_cfg, + SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); /* do a soft reset */ - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); /* now set rx and tx channel ON */ - setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + setbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); return 0; } @@ -104,7 +104,7 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) { int upto, todo; int i; - clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + clrbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ /* Send read instruction (0x3h) followed by a 24 bit addr */ write32(®s->tx_data, (SF_READ_DATA_CMD << 24) | off); @@ -117,7 +117,7 @@ int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off) exynos_spi_rx_tx(regs, todo, dest, (void *)(off), i); } - setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + setbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ return len; } @@ -128,17 +128,17 @@ int exynos_spi_close(struct exynos_spi *regs) * Let put controller mode to BYTE as * SPI driver does not support WORD mode yet */ - clrbits_le32(®s->mode_cfg, - SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); + clrbits32(®s->mode_cfg, + SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD); write32(®s->swap_cfg, 0); /* * Flush spi tx, rx fifos and reset the SPI controller * and clear rx/tx channel */ - clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); + clrsetbits32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); return 0; } diff --git a/src/soc/samsung/exynos5250/usb.c b/src/soc/samsung/exynos5250/usb.c index 076e42eee9..12b658aef3 100644 --- a/src/soc/samsung/exynos5250/usb.c +++ b/src/soc/samsung/exynos5250/usb.c @@ -25,9 +25,9 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) { - setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ - setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ - setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ + setbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } void reset_usb_drd_dwc3() @@ -77,7 +77,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) /* Set all PHY registers to default values */ /* XHCI Version 1.0, Frame Length adjustment 30 MHz */ - setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); + setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ write32(&phy->utmi, 1 << 6); @@ -120,13 +120,13 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->resume, 0x0); udelay(10); - clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ + clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } void setup_usb_drd_phy() { printk(BIOS_DEBUG, "Powering up USB DRD PHY\n"); - setbits_le32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd_phy); } @@ -134,8 +134,8 @@ void setup_usb_host_phy(int hsic_gpio) { unsigned int hostphy_ctrl0; - setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); - setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); + setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); @@ -156,13 +156,13 @@ void setup_usb_host_phy(int hsic_gpio) HOST_CTRL0_UTMISWRST); write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); - clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, - HOST_CTRL0_LINKSWRST | - HOST_CTRL0_UTMISWRST); + clrbits32(&exynos_usb_host_phy->usbphyctrl0, + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); udelay(20); /* EHCI Ctrl setting */ - setbits_le32(&exynos_usb_host_phy->ehcictrl, + setbits32(&exynos_usb_host_phy->ehcictrl, EHCICTRL_ENAINCRXALIGN | EHCICTRL_ENAINCR4 | EHCICTRL_ENAINCR8 | @@ -175,15 +175,15 @@ void setup_usb_host_phy(int hsic_gpio) gpio_direction_output(hsic_gpio, 1); udelay(5000); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_SIDDQ | - HOST_CTRL0_FORCESLEEP | - HOST_CTRL0_FORCESUSPEND); - setbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); udelay(10); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); } /* At this point we need to wait for 50ms before talking to diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index b578133ea4..fe11cdecff 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -390,7 +390,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) @@ -425,7 +425,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor) periph_id); return; } - clrsetbits_le32(reg, mask << shift, (divisor & mask) << shift); + clrsetbits32(reg, mask << shift, (divisor & mask) << shift); } /** @@ -607,7 +607,7 @@ int clock_epll_set_rate(unsigned long rate) void clock_select_i2s_clk_source(void) { - clrsetbits_le32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK, + clrsetbits32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK, (CLK_SRC_SCLK_EPLL)); } @@ -627,7 +627,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq); return -1; } - clrsetbits_le32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK, + clrsetbits32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK, (div & AUDIO_1_RATIO_MASK)); return 0; } diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index eae08a8dea..92abf32081 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -42,7 +42,7 @@ void system_clock_init(void) write32(&exynos_clock->kpll_lock, KPLL_LOCK_VAL); write32(&exynos_clock->rpll_lock, RPLL_LOCK_VAL); - setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); + setbits32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK); write32(&exynos_clock->clk_src_top6, 0); @@ -52,7 +52,7 @@ void system_clock_init(void) write32(&exynos_clock->clk_div_cpu0, CLK_DIV_CPU0_VAL); /* switch A15 clock source to OSC clock before changing APLL */ - clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); + clrbits32(&exynos_clock->clk_src_cpu, APLL_FOUT); /* Set APLL */ write32(&exynos_clock->apll_con1, APLL_CON1_VAL); @@ -62,13 +62,13 @@ void system_clock_init(void) ; /* now it is safe to switch to APLL */ - setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT); + setbits32(&exynos_clock->clk_src_cpu, APLL_FOUT); write32(&exynos_clock->clk_src_kfc, SRC_KFC_HPM_SEL); write32(&exynos_clock->clk_div_kfc0, CLK_DIV_KFC_VAL); /* switch A7 clock source to OSC clock before changing KPLL */ - clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); + clrbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set KPLL*/ write32(&exynos_clock->kpll_con1, KPLL_CON1_VAL); @@ -78,7 +78,7 @@ void system_clock_init(void) ; /* now it is safe to switch to KPLL */ - setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT); + setbits32(&exynos_clock->clk_src_kfc, KPLL_FOUT); /* Set MPLL */ write32(&exynos_clock->mpll_con1, MPLL_CON1_VAL); diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index 6ea92ee36f..88dc18d2f6 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -33,10 +33,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) int i, chip; /* Enable PAUSE for DREX */ - setbits_le32(&exynos_clock->pause, ENABLE_BIT); + setbits32(&exynos_clock->pause, ENABLE_BIT); /* Enable BYPASS mode */ - setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); + setbits32(&exynos_clock->bpll_con1, BYPASS_EN); write32(&exynos_clock->clk_src_cdrex, MUX_BPLL_SEL_FOUTBPLL); do { @@ -44,7 +44,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) val &= BPLL_SEL_MASK; } while (val != FOUTBPLL); - clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN); + clrbits32(&exynos_clock->bpll_con1, BYPASS_EN); /* Specify the DDR memory type as DDR3 */ val = read32(&exynos_phy0_control->phy_con0); @@ -87,8 +87,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)) return SETUP_ERR_ZQ_CALIBRATION_FAILURE; - clrbits_le32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN); - clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); + clrbits32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN); + clrbits32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN); /* DQ Signal */ val = read32(&exynos_phy0_control->phy_con14); @@ -116,8 +116,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) val = read32(&exynos_drex1->phystatus); } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); - clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START); - clrbits_le32(&exynos_drex1->concontrol, DFI_INIT_START); + clrbits32(&exynos_drex0->concontrol, DFI_INIT_START); + clrbits32(&exynos_drex1->concontrol, DFI_INIT_START); update_reset_dll(exynos_drex0, mem->mem_type); update_reset_dll(exynos_drex1, mem->mem_type); @@ -205,8 +205,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) write32(&exynos_phy0_control->phy_con0, PHY_CON0_RESET_VAL); write32(&exynos_phy1_control->phy_con0, PHY_CON0_RESET_VAL); - setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN); - setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN); + setbits32(&exynos_phy0_control->phy_con0, P0_CMD_EN); + setbits32(&exynos_phy1_control->phy_con0, P0_CMD_EN); val = PHY_CON2_RESET_VAL; val |= INIT_DESKEW_EN; @@ -243,11 +243,11 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) val | (chip << DIRECT_CMD_CHIP_SHIFT)); } - setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); - setbits_le32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN); + setbits32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN); + setbits32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN); - setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); - setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); + setbits32(&exynos_phy0_control->phy_con0, CTRL_SHGATE); + setbits32(&exynos_phy1_control->phy_con0, CTRL_SHGATE); val = read32(&exynos_phy0_control->phy_con1); val &= ~(CTRL_GATEDURADJ_MASK); @@ -303,8 +303,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) write32(&exynos_phy0_control->phy_con12, (val + nLockW_phy0)); write32(&exynos_phy1_control->phy_con12, (val + nLockW_phy1)); - setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); - setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); + setbits32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN); + setbits32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN); } /* Send PALL command */ @@ -332,8 +332,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset) * this saves around 25 mw dmc power as compared to the power * consumption without these bits enabled */ - setbits_le32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG); - setbits_le32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG); + setbits32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG); + setbits32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG); return 0; } diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index 9dfffd6ee6..b59162eccd 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -25,7 +25,7 @@ static void ps_hold_setup(void) { /* Set PS-Hold high */ - setbits_le32(&exynos_power->ps_hold_ctrl, + setbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); } @@ -34,13 +34,13 @@ void power_reset(void) /* Clear inform1 so there's no change we think we've got a wake reset */ exynos_power->inform1 = 0; - setbits_le32(&exynos_power->sw_reset, 1); + setbits32(&exynos_power->sw_reset, 1); } /* This function never returns */ void power_shutdown(void) { - clrbits_le32(&exynos_power->ps_hold_ctrl, + clrbits32(&exynos_power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH); halt(); @@ -48,13 +48,13 @@ void power_shutdown(void) void power_enable_dp_phy(void) { - setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); + setbits32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE); } void power_enable_hw_thermal_trip(void) { /* Enable HW thermal trip */ - setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); + setbits32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); } uint32_t power_read_reset_status(void) @@ -78,7 +78,7 @@ int power_init(void) void power_enable_xclkout(void) { /* use xxti for xclk out */ - clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + clrsetbits32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, PMU_DEBUG_XXTI); } diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 1903f6b3b9..5637b0215d 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -89,10 +89,10 @@ static void spi_sw_reset(struct exynos_spi *regs, int word) if (swap_cfg != orig_swap_cfg) write32(®s->swap_cfg, swap_cfg); - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->ch_cfg, SPI_CH_RST); - clrbits_le32(®s->ch_cfg, SPI_CH_RST); - setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + setbits32(®s->ch_cfg, SPI_CH_RST); + clrbits32(®s->ch_cfg, SPI_CH_RST); + setbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); } static void exynos_spi_init(struct exynos_spi *regs) @@ -100,14 +100,14 @@ static void exynos_spi_init(struct exynos_spi *regs) // Set FB_CLK_SEL. write32(®s->fb_clk, SPI_FB_DELAY_180); // CPOL: Active high. - clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); + clrbits32(®s->ch_cfg, SPI_CH_CPOL_L); // Clear rx and tx channel if set priveously. - clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + clrbits32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - setbits_le32(®s->swap_cfg, + setbits32(®s->swap_cfg, SPI_RX_SWAP_EN | SPI_RX_BYTE_SWAP | SPI_RX_HWORD_SWAP); - clrbits_le32(®s->ch_cfg, SPI_CH_HS_EN); + clrbits32(®s->ch_cfg, SPI_CH_HS_EN); // Do a soft reset, which will also enable both channels. spi_sw_reset(regs, 1); @@ -117,7 +117,7 @@ static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; // TODO(hungte) Add some delay if too many transactions happen at once. - clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); + clrbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); return 0; } @@ -201,7 +201,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_ static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; - setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); + setbits32(®s->cs_reg, SPI_SLAVE_SIG_INACT); } static int spi_ctrlr_setup(const struct spi_slave *slave) diff --git a/src/soc/samsung/exynos5420/usb.c b/src/soc/samsung/exynos5420/usb.c index 9dda4c100d..2f141c1b67 100644 --- a/src/soc/samsung/exynos5420/usb.c +++ b/src/soc/samsung/exynos5420/usb.c @@ -25,9 +25,9 @@ static void reset_dwc3(struct exynos5_usb_drd_dwc3 *dwc3) { - setbits_le32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ - setbits_le32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ - setbits_le32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->ctl, 0x1 << 11); /* core soft reset */ + setbits32(&dwc3->usb3pipectl, 0x1 << 31); /* PHY soft reset */ + setbits32(&dwc3->usb2phycfg, 0x1 << 31); /* PHY soft reset */ } void reset_usb_drd0_dwc3() @@ -89,7 +89,7 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) /* Set all PHY registers to default values */ /* XHCI Version 1.0, Frame Length adjustment 30 MHz */ - setbits_le32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); + setbits32(&phy->linksystem, 0x1 << 27 | 0x20 << 1); /* Disable OTG, ID0 and DRVVBUS, do not force sleep/suspend */ write32(&phy->utmi, 1 << 6); @@ -132,20 +132,20 @@ static void setup_drd_phy(struct exynos5_usb_drd_phy *phy) write32(&phy->resume, 0x0); udelay(10); - clrbits_le32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ + clrbits32(&phy->clkrst, 0x1 << 1); /* deassert port reset */ } void setup_usb_drd0_phy() { printk(BIOS_DEBUG, "Powering up USB DRD0 PHY\n"); - setbits_le32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd0_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd0_phy); } void setup_usb_drd1_phy() { printk(BIOS_DEBUG, "Powering up USB DRD1 PHY\n"); - setbits_le32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_power->usb_drd1_phy_ctrl, POWER_USB_PHY_CTRL_EN); setup_drd_phy(exynos_usb_drd1_phy); } @@ -153,8 +153,8 @@ void setup_usb_host_phy(int hsic_gpio) { unsigned int hostphy_ctrl0; - setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); - setbits_le32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); + setbits32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN); + setbits32(&exynos_power->usb_host_phy_ctrl, POWER_USB_PHY_CTRL_EN); printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n", hsic_gpio ? "with" : "without"); @@ -175,17 +175,17 @@ void setup_usb_host_phy(int hsic_gpio) HOST_CTRL0_UTMISWRST); write32(&exynos_usb_host_phy->usbphyctrl0, hostphy_ctrl0); udelay(10); - clrbits_le32(&exynos_usb_host_phy->usbphyctrl0, - HOST_CTRL0_LINKSWRST | - HOST_CTRL0_UTMISWRST); + clrbits32(&exynos_usb_host_phy->usbphyctrl0, + HOST_CTRL0_LINKSWRST | + HOST_CTRL0_UTMISWRST); udelay(20); /* EHCI Ctrl setting */ - setbits_le32(&exynos_usb_host_phy->ehcictrl, - EHCICTRL_ENAINCRXALIGN | - EHCICTRL_ENAINCR4 | - EHCICTRL_ENAINCR8 | - EHCICTRL_ENAINCR16); + setbits32(&exynos_usb_host_phy->ehcictrl, + EHCICTRL_ENAINCRXALIGN | + EHCICTRL_ENAINCR4 | + EHCICTRL_ENAINCR8 | + EHCICTRL_ENAINCR16); /* HSIC USB Hub initialization. */ if (hsic_gpio) { @@ -194,15 +194,15 @@ void setup_usb_host_phy(int hsic_gpio) gpio_direction_output(hsic_gpio, 1); udelay(5000); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_SIDDQ | - HOST_CTRL0_FORCESLEEP | - HOST_CTRL0_FORCESUSPEND); - setbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_SIDDQ | + HOST_CTRL0_FORCESLEEP | + HOST_CTRL0_FORCESUSPEND); + setbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); udelay(10); - clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1, - HOST_CTRL0_PHYSWRST); + clrbits32(&exynos_usb_host_phy->hsicphyctrl1, + HOST_CTRL0_PHYSWRST); } /* At this point we need to wait for 50ms before talking to diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 60a8a134c3..ef6221b262 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -84,7 +84,7 @@ static void configure_pll(u32 *reg, const struct pll_settings *s) { // Write the settings to the register u32 c = read32(reg); - clrsetbits_le32(&c, PRCI_PLLCFG_DIVR_MASK + clrsetbits32(&c, PRCI_PLLCFG_DIVR_MASK | PRCI_PLLCFG_DIVF_MASK | PRCI_PLLCFG_DIVQ_MASK | PRCI_PLLCFG_RANGE_MASK | PRCI_PLLCFG_BYPASS_MASK | PRCI_PLLCFG_FSE_MASK, @@ -155,13 +155,13 @@ static const struct pll_settings gemgxlpll_settings = { static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL - clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, + clrsetbits32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_HFCLK); configure_pll(&prci->corepllcfg0, &corepll_settings); // switch coreclk to use corepll - clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, + clrsetbits32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_CORE_PLL); } @@ -169,25 +169,25 @@ static void init_pll_ddr(void) { // disable ddr clock output before reconfiguring the PLL u32 cfg1 = read32(&prci->ddrpllcfg1); - clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); + clrbits32(&cfg1, PRCI_DDRPLLCFG1_MASK); write32(&prci->ddrpllcfg1, cfg1); configure_pll(&prci->ddrpllcfg0, &ddrpll_settings); // enable ddr clock output - setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); + setbits32(&cfg1, PRCI_DDRPLLCFG1_MASK); write32(&prci->ddrpllcfg1, cfg1); } static void init_gemgxlclk(void) { u32 cfg1 = read32(&prci->gemgxlpllcfg1); - clrbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + clrbits32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); write32(&prci->gemgxlpllcfg1, cfg1); configure_pll(&prci->gemgxlpllcfg0, &gemgxlpll_settings); - setbits_le32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); + setbits32(&cfg1, PRCI_GEMGXLPPLCFG1_MASK); write32(&prci->gemgxlpllcfg1, cfg1); } diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index 5e30e77939..ae57cf6ef0 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <arch/mmio.h> +#include <device/mmio.h> #include <soc/spi.h> #include <soc/clock.h> #include <soc/addressmap.h> |