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authorNaveen Krishna Chatradhi <naveenkrishna.ch@intel.com>2015-07-15 16:02:25 +0530
committerPatrick Georgi <pgeorgi@google.com>2015-07-21 20:10:19 +0200
commit5c56ce13f4a81970ed8c9a2987c2ea55376da52d (patch)
treeba4508864e22ca5ca14cfa912147081e0fffee28 /src/soc
parentbbbfbf2e0fe3c1af135a955505b6a2fd73681a8e (diff)
downloadcoreboot-5c56ce13f4a81970ed8c9a2987c2ea55376da52d.tar.xz
Skylake: Only support UART2 as debug port, clean up the rest
On Skylake, only UART2 is supported as debug port and the macros INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and Glados boards. BRANCH=none BUG=chrome-os-partner:40857 TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2 Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642 Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285793 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-on: http://review.coreboot.org/10994 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/Kconfig15
-rw-r--r--src/soc/intel/skylake/romstage/Makefile.inc2
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c3
-rw-r--r--src/soc/intel/skylake/romstage/uart.c26
-rw-r--r--src/soc/intel/skylake/uart.c13
5 files changed, 10 insertions, 49 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 207816d30d..856b84fa1f 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select CACHE_ROM
select CAR_MIGRATION
+ select CONSOLE_SERIAL8250MEM
select COLLECT_TIMESTAMPS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_MICROCODE_IN_CBFS
@@ -24,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_HARD_RESET
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
+ select HAVE_UART_MEMORY_MAPPED
select IOAPIC
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
@@ -160,18 +162,6 @@ config IFD_PLATFORM_SECTION
string
default ""
-config INTEL_PCH_UART_CONSOLE
- bool "Use Serial IO UART for console"
- default n
- select HAVE_UART_MEMORY_MAPPED
- select CONSOLE_SERIAL8250MEM
- depends on !CONFIG_DRIVERS_OXFORD_OXPCIE
-
-config INTEL_PCH_UART_CONSOLE_NUMBER
- hex "Serial IO UART number to use for console"
- default "0x0"
- depends on INTEL_PCH_UART_CONSOLE
-
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
@@ -222,7 +212,6 @@ config SMM_TSEG_SIZE
config TTYS0_BASE
hex
default 0xfe034000
- depends on INTEL_PCH_UART_CONSOLE
config VGA_BIOS_ID
string
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 52029fcf78..68467b5ab0 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -6,4 +6,4 @@ romstage-y += romstage.c
romstage-y += smbus.c
romstage-y += spi.c
romstage-y += systemagent.c
-romstage-$(CONFIG_INTEL_PCH_UART_CONSOLE) += uart.c
+romstage-y += uart.c
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 4230664911..919b747211 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -50,8 +50,7 @@ void soc_pre_console_init(struct romstage_params *params)
/* System Agent Early Initialization */
systemagent_early_init();
- if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
- pch_uart_init();
+ pch_uart_init();
}
/* SOC initialization before RAM is enabled */
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c
index 8ddcbadda8..8aa1053150 100644
--- a/src/soc/intel/skylake/romstage/uart.c
+++ b/src/soc/intel/skylake/romstage/uart.c
@@ -28,27 +28,10 @@
void pch_uart_init(void)
{
- device_t dev;
- u32 tmp, legacy;
+ device_t dev = PCH_DEV_UART2;
+ u32 tmp;
u8 *base = (u8 *)CONFIG_TTYS0_BASE;
- switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
- case 0:
- dev = PCH_DEV_UART0;
- legacy = SIO_PCH_LEGACY_UART0;
- break;
- case 1:
- dev = PCH_DEV_UART1;
- legacy = SIO_PCH_LEGACY_UART1;
- break;
- case 2:
- dev = PCH_DEV_UART2;
- legacy = SIO_PCH_LEGACY_UART2;
- break;
- default:
- return;
- }
-
/* Set configured UART base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
@@ -70,6 +53,7 @@ void pch_uart_init(void)
(SIO_REG_PPR_CLOCK_M_DIV << 1);
write32(base + SIO_REG_PPR_CLOCK, tmp);
- /* Put UART in byte access mode for 16550 compatibility */
- pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, legacy);
+ /* Put UART2 in byte access mode for 16550 compatibility */
+ pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0,
+ SIO_PCH_LEGACY_UART2);
}
diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
index 36b1b5a71b..03d2ba6a7c 100644
--- a/src/soc/intel/skylake/uart.c
+++ b/src/soc/intel/skylake/uart.c
@@ -28,18 +28,7 @@
static int pch_uart_is_debug(struct device *dev)
{
- if (!IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
- return 0;
-
- switch (dev->path.pci.devfn) {
- case PCH_DEVFN_UART0:
- return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0;
- case PCH_DEVFN_UART1:
- return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1;
- case PCH_DEVFN_UART2:
- return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 2;
- }
- return 0;
+ return dev->path.pci.devfn == PCH_DEVFN_UART2;
}
static void pch_uart_read_resources(struct device *dev)