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authorRob Barnes <robbarnes@google.com>2020-09-01 10:28:36 -0600
committerAaron Durbin <adurbin@chromium.org>2020-09-03 21:28:13 +0000
commitb132bf5a87784a8a57677f43607095330be9f3a1 (patch)
treeede0b74f02c6c44a0f8f06dc4bdade39c9d0dfbc /src/soc
parent327f1058d2feaa022407128aa9dac55f408b714c (diff)
downloadcoreboot-b132bf5a87784a8a57677f43607095330be9f3a1.tar.xz
soc/amd/picasso: Set max_speed_mts and configured_speed_mts
ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts instead. This will result in SMBIOS type 17 displaying more accurate speed information. BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/picasso/dmi.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c
index 3988616896..5189cd6ac4 100644
--- a/src/soc/amd/picasso/dmi.c
+++ b/src/soc/amd/picasso/dmi.c
@@ -28,14 +28,12 @@ static void transfer_memory_info(const TYPE17_DMI_INFO *dmi17,
dimm->ddr_type = dmi17->MemoryType;
/**
- * Based on the name, ddr_frequency should hold the memory clock
- * frequency in MHz. However it is interpreted as MT/s in SMBIOS
- * downstream. So multiply by 2 to translate to memory speed in MT/s.
- * ddr_frequency is used for setting both config speed and max
- * speed. Using config speed so we don't get the false impression
- * that the RAM is running faster than it actually is.
+ * TYPE17_DMI_INFO holds speed in MHz.
+ * Change to MT/s by multiplying by 2.
*/
- dimm->ddr_frequency = 2 * dmi17->ConfigSpeed;
+ dimm->configured_speed_mts = 2 * dmi17->ConfigSpeed;
+
+ dimm->max_speed_mts = 2 * dmi17->Speed;
dimm->rank_per_dimm = dmi17->Attributes;