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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-28 09:42:47 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 06:18:13 +0000
commitb30d0545843b6ba3e8c0976a1fc0f1413be1608b (patch)
tree41c27030e6e7521a3839cddf19b6d375a535f71f /src/soc
parenta15eaec1e6975d78687aaea06996464b5a67f14c (diff)
downloadcoreboot-b30d0545843b6ba3e8c0976a1fc0f1413be1608b.tar.xz
soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/stoneyridge/psp.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index 88bd61d4dd..5a4cd4dbab 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -12,7 +12,8 @@
void soc_enable_psp_early(void)
{
- u32 base, limit, cmd;
+ u32 base, limit;
+ u16 cmd;
/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
@@ -25,9 +26,9 @@ void soc_enable_psp_early(void)
pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
/* Enable memory access and master */
- cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
+ cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND);
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
+ pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
};
void *soc_get_mbox_address(void)