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authorDuncan Laurie <dlaurie@chromium.org>2015-08-27 16:03:45 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-08 11:17:01 +0000
commitbf9df75eac002296b570620f824d7bf7011de1e4 (patch)
tree3c19a316d8775fe598c029ae801e6424d8182442 /src/soc
parent86d937fb46bfb3b4d5c850b28e79ff25cb56faa4 (diff)
downloadcoreboot-bf9df75eac002296b570620f824d7bf7011de1e4.tar.xz
skylake: ACPI: Add functions for PCR access
There are a few places in ACPI that touch PCR registers, either to read a value or to set some magic bits. Expose some functions for this that will keep all the PCR access in one location instead of spread throughout the code. BUG=chrome-os-partner:44622 BRANCH=none TEST=emerge-glados coreboot Change-Id: Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e78b2801fbc5c00ba452ae5e4ecb07c3e23bf6c1 Original-Change-Id: I2e4d491157f7ac6d2ebc231b11661c059b4a7fa0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295904 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11531 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/skylake/acpi/pch.asl2
-rw-r--r--src/soc/intel/skylake/acpi/pcr.asl75
2 files changed, 77 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index 18a41f25b3..581efa082b 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -37,6 +37,8 @@
/* PCIE Ports */
#include "pcie.asl"
+/* PCR Access */
+#include "pcr.asl"
/* Serial IO */
#include "serialio.asl"
diff --git a/src/soc/intel/skylake/acpi/pcr.asl b/src/soc/intel/skylake/acpi/pcr.asl
new file mode 100644
index 0000000000..a6fb46e0b1
--- /dev/null
+++ b/src/soc/intel/skylake/acpi/pcr.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/*
+ * Calculate PCR register base at specified PID
+ * Arg0 - PCR Port ID
+ */
+Method (PCRB, 1, NotSerialized)
+{
+ Return (Add (PCH_PCR_BASE_ADDRESS, ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
+}
+
+/*
+ * Read a PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ */
+Method (PCRR, 2, NotSerialized)
+{
+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+ Field (PCRD, DWordAcc, NoLock, Preserve)
+ {
+ DATA, 32
+ }
+ Return (DATA)
+}
+
+/*
+ * AND a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to AND
+ */
+Method (PCRA, 3, Serialized)
+{
+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+ Field (PCRD, DWordAcc, NoLock, Preserve)
+ {
+ DATA, 32
+ }
+ And (DATA, Arg2, DATA)
+}
+
+/*
+ * OR a value with PCR register at specified PID and offset
+ * Arg0 - PCR Port ID
+ * Arg1 - Register Offset
+ * Arg2 - Value to OR
+ */
+Method (PCRO, 3, Serialized)
+{
+ OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
+ Field (PCRD, DWordAcc, NoLock, Preserve)
+ {
+ DATA, 32
+ }
+ Or (DATA, Arg2, DATA)
+}