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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-17 20:51:08 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-26 21:08:41 +0000
commitcd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch)
treeb0438431df0943ab5f0fa9d80a99fc265130ac23 /src/soc
parent16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff)
downloadcoreboot-cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf.tar.xz
soc/intel: Use common romstage code
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/romstage.c29
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c19
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c1
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c20
-rw-r--r--src/soc/intel/denverton_ns/romstage.c32
-rw-r--r--src/soc/intel/icelake/romstage/romstage.c20
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c26
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c47
8 files changed, 67 insertions, 127 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 1464d2c6b3..2c283396c9 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -16,7 +16,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <device/pci_ops.h>
#include <arch/symbols.h>
@@ -193,20 +192,15 @@ void set_max_freq(void)
cpu_set_p_state_to_turbo_ratio();
}
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
bool s3wake;
+ size_t var_size;
struct chipset_power_state *ps = pmc_get_power_state();
- uintptr_t smm_base;
- size_t smm_size, var_size;
const void *new_var_data;
timestamp_add_now(TS_START_ROMSTAGE);
- console_init();
-
soc_early_romstage_init();
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
@@ -227,10 +221,14 @@ asmlinkage void car_stage_entry(void)
else
printk(BIOS_ERR, "Failed to determine variable data\n");
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
-
mainboard_save_dimm_info();
+}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t smm_base;
+ size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this point exact
@@ -240,12 +238,9 @@ asmlinkage void car_stage_entry(void)
top_of_ram = (uintptr_t) cbmem_top();
/* cbmem_top() needs to be at least 16 MiB aligned */
assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
- /* Cache the memory-mapped boot media. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
@@ -254,9 +249,7 @@ asmlinkage void car_stage_entry(void)
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
-
- run_postcar_phase(&pcf);
+ postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
}
static void fill_console_params(FSPM_UPD *mupd)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index f20c363a35..aa9fa6b66a 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -54,23 +54,6 @@
static struct postcar_frame early_mtrrs;
-static void fill_postcar_frame(struct postcar_frame *pcf);
-
-/* prepare_and_run_postcar() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-static void prepare_and_run_postcar(struct postcar_frame *pcf)
-{
- if (postcar_frame_init(pcf, 0))
- die("Unable to initialize postcar frame.\n");
-
- fill_postcar_frame(pcf);
-
- postcar_frame_common_mtrrs(pcf);
-
- run_postcar_phase(pcf);
- /* We do not return here. */
-}
-
static void program_base_addresses(void)
{
uint32_t reg;
@@ -260,7 +243,7 @@ void romstage_common(struct romstage_params *params)
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
-static void fill_postcar_frame(struct postcar_frame *pcf)
+void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 3f264ff5ec..b3662e1591 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -21,7 +21,6 @@
#include <bootmode.h>
#include <cbmem.h>
#include <console/console.h>
-#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <elog.h>
#include <program_loading.h>
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 9f02c8b1d3..5711c15142 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
@@ -128,15 +127,11 @@ static void save_dimm_info(void)
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
bool s3wake;
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
struct chipset_power_state *ps = pmc_get_power_state();
- console_init();
-
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* initialize Heci interface */
@@ -148,9 +143,11 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
+}
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
@@ -160,10 +157,5 @@ asmlinkage void car_stage_entry(void)
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
- run_postcar_phase(&pcf);
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 9c41486aa2..cbd451ae0d 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <arch/io.h>
#include <cbmem.h>
@@ -137,16 +136,8 @@ static void early_tco_init(void)
outw(reg16, tco_base + TCO2_STS);
}
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
-
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
- uintptr_t smm_base;
- size_t smm_size;
-
- console_init();
-
printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n");
mainboard_config_gpios();
@@ -158,9 +149,13 @@ asmlinkage void car_stage_entry(void)
#if CONFIG(DISPLAY_HOBS)
display_fsp_smbios_memory_info_hob();
#endif
+}
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t smm_base;
+ size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this point exact
@@ -168,12 +163,9 @@ asmlinkage void car_stage_entry(void)
* 16 megs under cbmem top which is a safe bet to cover ramstage.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
MTRR_TYPE_WRBACK);
- /* Cache the memory-mapped boot media. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
@@ -181,12 +173,8 @@ asmlinkage void car_stage_entry(void)
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
- if (CONFIG(HAVE_SMI_HANDLER)) {
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
- }
-
- run_postcar_phase(&pcf);
+ smm_region(&smm_base, &smm_size);
+ postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
}
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 8312f178e4..67ef2bb6ce 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <cpu/x86/mtrr.h>
#include <cbmem.h>
@@ -112,15 +111,11 @@ static void save_dimm_info(void)
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
bool s3wake;
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
struct chipset_power_state *ps = pmc_get_power_state();
- console_init();
-
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* initialize Heci interface */
@@ -132,9 +127,11 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
+}
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
@@ -144,10 +141,5 @@ asmlinkage void car_stage_entry(void)
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
- run_postcar_phase(&pcf);
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
}
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 0489621045..bd30271d77 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -28,12 +28,11 @@
#include <soc/reg_access.h>
#include <soc/storage_test.h>
+static struct postcar_frame early_mtrrs;
+
asmlinkage void car_stage_c_entry(void)
{
- struct postcar_frame pcf;
bool s3wake;
- uintptr_t top_of_ram;
- uintptr_t top_of_low_usable_memory;
post_code(0x20);
console_init();
@@ -63,28 +62,33 @@ asmlinkage void car_stage_c_entry(void)
/* Initialize the PCIe bridges */
pcie_init();
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
+ prepare_and_run_postcar(&early_mtrrs);
+ /* We do not return here. */
+}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t top_of_low_usable_memory;
/* Locate the top of RAM */
top_of_low_usable_memory = (uintptr_t) cbmem_top();
top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
/* Cache postcar and ramstage */
- postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB,
+ postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
MTRR_TYPE_WRBACK);
/* Cache RMU area */
- postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory,
+ postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
0x10000, MTRR_TYPE_WRTHROUGH);
/* Cache ESRAM */
- postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
+ pcf->skip_common_mtrr = 1;
/* Cache SPI flash - Write protect not supported */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH);
-
- run_postcar_phase(&pcf);
+ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
}
static struct chipset_power_state power_state;
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 8b5cd18195..2412f22a27 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-#include <arch/cpu.h>
#include <arch/romstage.h>
#include <arch/symbols.h>
#include <assert.h>
@@ -140,15 +139,11 @@ static void save_dimm_info(void)
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
-asmlinkage void car_stage_entry(void)
+void mainboard_romstage_entry(void)
{
bool s3wake;
- struct postcar_frame pcf;
- uintptr_t top_of_ram;
struct chipset_power_state *ps;
- console_init();
-
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
@@ -159,8 +154,13 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 0))
- die("Unable to initialize postcar frame.\n");
+}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+ uintptr_t top_of_ram;
+ uintptr_t smm_base;
+ size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this
@@ -171,28 +171,17 @@ asmlinkage void car_stage_entry(void)
top_of_ram = (uintptr_t) cbmem_top();
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
top_of_ram -= 16*MiB;
- postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-
- if (CONFIG(HAVE_SMI_HANDLER)) {
- uintptr_t smm_base;
- size_t smm_size;
+ postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
- /*
- * Cache the TSEG region at the top of ram. This region is
- * not restricted to SMM mode until SMM has been relocated.
- * By setting the region to cacheable it provides faster access
- * when relocating the SMM handler as well as using the TSEG
- * region for other purposes.
- */
- smm_region(&smm_base, &smm_size);
- postcar_frame_add_mtrr(&pcf, smm_base, smm_size,
- MTRR_TYPE_WRBACK);
- }
-
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
-
- run_postcar_phase(&pcf);
+ /*
+ * Cache the TSEG region at the top of ram. This region is
+ * not restricted to SMM mode until SMM has been relocated.
+ * By setting the region to cacheable it provides faster access
+ * when relocating the SMM handler as well as using the TSEG
+ * region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
}
static void cpu_flex_override(FSP_M_CONFIG *m_cfg)