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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-05-26 09:31:41 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-28 09:30:35 +0000 |
| commit | de27499b520fb8bf5ec63da8dd582e7b1ef023c3 (patch) | |
| tree | 8ebf7cee33ad94a192951faef4672c7bffe689dc /src/soc | |
| parent | 333ba2aadd9f2f619d0961ed270f9c83e6e048d6 (diff) | |
| download | coreboot-de27499b520fb8bf5ec63da8dd582e7b1ef023c3.tar.xz | |
soc/ucb/riscv: Add chip_operations stub
Change-Id: Ie4f70429c516fff613d372fec7c1c955645f1c6d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/ucb/riscv/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/ucb/riscv/chip.c | 7 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index 80899d570f..6d2c36a340 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -4,4 +4,6 @@ romstage-y += cbmem.c ramstage-y += cbmem.c +ramstage-y += chip.c + endif diff --git a/src/soc/ucb/riscv/chip.c b/src/soc/ucb/riscv/chip.c new file mode 100644 index 0000000000..187e96d274 --- /dev/null +++ b/src/soc/ucb/riscv/chip.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations soc_ucb_riscv_ops = { + CHIP_NAME("UCB RISC-V") +}; |