diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-12-24 16:35:13 +0800 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 14:47:59 +0000 |
| commit | e6ac20b9d019a90ecaf330cebba94a1fe690db62 (patch) | |
| tree | aca435f5128a74fbdedbb7016f9984e9028a7b56 /src/soc | |
| parent | 2d68cec918327932e42844b16d169d9e0382aa56 (diff) | |
| download | coreboot-e6ac20b9d019a90ecaf330cebba94a1fe690db62.tar.xz | |
soc/mediatek/mt8183: Restore vcore after DRAM calibration
DRAM calibration sets vcore to different voltages at different
frequencies. After DRAM calibration, vcore should be restored to the
default voltage, which is 800mV for both eMCP and discrete DDR devices.
BRANCH=kukui
BUG=b:146618163
TEST=bootup pass
Change-Id: Ia87b4ac78a32dbd4c4ab52e84d307cb46525afa1
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8183/memory.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 13c3d9ad36..78890ea3d2 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -21,6 +21,7 @@ #include <soc/dramc_param.h> #include <soc/dramc_pi_api.h> #include <soc/emi.h> +#include <soc/mt6358.h> #include <symbols.h> static int mt_mem_test(void) @@ -156,7 +157,7 @@ static void init_sdram_params(struct sdram_params *dst, memcpy(&dst[shuffle], src, sizeof(*dst)); } -void mt_mem_init(struct dramc_param_ops *dparam_ops) +static void mt_mem_init_run(struct dramc_param_ops *dparam_ops) { struct dramc_param *dparam = dparam_ops->param; @@ -202,6 +203,7 @@ void mt_mem_init(struct dramc_param_ops *dparam_ops) if (err == 0) { printk(BIOS_INFO, "Successfully loaded DRAM blobs and " "ran DRAM calibration\n"); + /* * In recovery mode the system boots in RO but the flash params * should be calibrated for RW so we can't mix them up. @@ -228,3 +230,11 @@ void mt_mem_init(struct dramc_param_ops *dparam_ops) if (mt_mem_test() != 0) die("Memory test failed with params from sdram config\n"); } + +void mt_mem_init(struct dramc_param_ops *dparam_ops) +{ + mt_mem_init_run(dparam_ops); + + /* After DRAM calibration, restore vcore voltage to default setting */ + pmic_set_vcore_vol(800000); +} |