soc/intel/xeon_sp: Enable LPC generic IO decode range

To use Intel common block LPC function that enables the IO ranges
defined in devicetree.cb.

Tested on OCP Tioga Pass with BMC LPC working.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 33 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 3178a4e2bf..59350bf967 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -24,6 +24,7 @@ subdirs-y += ../../../cpu/x86/cache
 subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
 
 bootblock-y += bootblock/bootblock.c
+bootblock-y += lpc.c
 bootblock-y += spi.c
 
 postcar-y += soc_util.c
diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c
index dc88adc308..453c383897 100644
--- a/src/soc/intel/xeon_sp/bootblock/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c
@@ -20,6 +20,7 @@
 #include <soc/iomap.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
+#include <intelblocks/lpc_lib.h>
 
 const FSPT_UPD temp_ram_init_params = {
 	.FspUpdHeader = {
@@ -52,6 +53,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 void bootblock_soc_early_init(void)
 {
 	fast_spi_early_init(SPI_BASE_ADDRESS);
+	pch_enable_lpc();
 }
 
 void bootblock_soc_init(void)
diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h
index 9388ba5407..94726f35eb 100644
--- a/src/soc/intel/xeon_sp/chip.h
+++ b/src/soc/intel/xeon_sp/chip.h
@@ -76,6 +76,12 @@ struct soc_intel_xeon_sp_config {
 	uint32_t vtd_support;
 	uint32_t coherency_support;
 	uint32_t ats_support;
+
+	/* Generic IO decode ranges */
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
+	uint32_t gen3_dec;
+	uint32_t gen4_dec;
 };
 
 extern struct chip_operations soc_intel_xeon_sp_ops;
diff --git a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h
index 8d898e6e4e..8d53ab77e2 100644
--- a/src/soc/intel/xeon_sp/include/soc/pcr_ids.h
+++ b/src/soc/intel/xeon_sp/include/soc/pcr_ids.h
@@ -18,5 +18,6 @@
 
 #define PID_ITSS      0xC4
 #define PID_RTC       0xC3
+#define PID_DMI       0xEF
 
 #endif	/* _PCR_IDS_H_ */
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c
index 4dd6f7c657..6dc2c41fe0 100644
--- a/src/soc/intel/xeon_sp/lpc.c
+++ b/src/soc/intel/xeon_sp/lpc.c
@@ -16,8 +16,12 @@
 #include <console/console.h>
 #include <arch/ioapic.h>
 #include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
 #include <soc/soc_util.h>
 #include <soc/iomap.h>
+#include <soc/pcr_ids.h>
+
+#include "chip.h"
 
 static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = {
 	{ 0, 0 }
@@ -28,6 +32,25 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
 	return xeon_lpc_fixed_mmio_ranges;
 }
 
+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
+{
+	const config_t *config = config_of(dev);
+
+	gen_io_dec[0] = config->gen1_dec;
+	gen_io_dec[1] = config->gen2_dec;
+	gen_io_dec[2] = config->gen3_dec;
+	gen_io_dec[3] = config->gen4_dec;
+}
+
+void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
+{
+	/* Mirror these same settings in DMI PCR */
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
+	pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
+}
+
 void lpc_soc_init(struct device *dev)
 {
 	printk(BIOS_SPEW, "pch: lpc_init\n");