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authorNico Huber <nico.huber@secunet.com>2017-05-22 15:58:03 +0200
committerNico Huber <nico.h@gmx.de>2017-06-08 14:58:29 +0200
commit2e7f6ccafc3e633ed9001b3c3863253ee0630429 (patch)
treef8e8ff0b026fe9adf97b7cdc135665044f614b5a /src/soc
parentd4ebeaf475dc1137f489f12ffa4e55d914238662 (diff)
downloadcoreboot-2e7f6ccafc3e633ed9001b3c3863253ee0630429.tar.xz
fsp/gop: Add running the GOP to the choice of gfx init
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/Kconfig3
-rw-r--r--src/soc/intel/braswell/Kconfig1
-rw-r--r--src/soc/intel/braswell/Makefile.inc5
-rw-r--r--src/soc/intel/braswell/acpi.c18
-rw-r--r--src/soc/intel/braswell/include/soc/acpi.h2
-rw-r--r--src/soc/intel/common/vbt.c3
-rw-r--r--src/soc/intel/skylake/Kconfig4
7 files changed, 17 insertions, 19 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index b0fd4b10a8..0a13a6659f 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -78,7 +78,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_GFX_OPREGION
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CSE
- select ADD_VBT_DATA_FILE
+ select ADD_VBT_DATA_FILE if RUN_FSP_GOP
+ select HAVE_FSP_GOP
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 61f41edd2c..520253add0 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS
select USE_GENERIC_FSP_CAR_INC
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
+ select HAVE_FSP_GOP
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc
index abd64a5ec0..88d024243b 100644
--- a/src/soc/intel/braswell/Makefile.inc
+++ b/src/soc/intel/braswell/Makefile.inc
@@ -20,7 +20,7 @@ ramstage-y += cpu.c
ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += emmc.c
ramstage-y += gpio.c
-ifeq ($(CONFIG_GOP_SUPPORT),n)
+ifneq ($(CONFIG_RUN_FSP_GOP),y)
ramstage-y += gfx.c
endif
ramstage-y += gpio_support.c
@@ -59,7 +59,6 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR)
-ifneq ($(CONFIG_GOP_SUPPORT),y)
ifneq ($(CONFIG_VGA_BIOS_FILE),)
#we will assume that the vbios names will remain as they are now: vgabios.bin and vgabios_c0.bin
BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FILE)))
@@ -67,8 +66,6 @@ BRASWELL_C0_VBIOS= $(subst .bin,_c0.bin,$(call strip_quotes,$(CONFIG_VGA_BIOS_FI
cbfs-files-$(CONFIG_VGA_BIOS) += pci8086,22b1.rom
pci8086,22b1.rom-file := $(BRASWELL_C0_VBIOS)
pci8086,22b1.rom-type := optionrom
-
-endif # ifneq ($(CONFIG_GOP_SUPPORT),y)
endif # ifneq ($(CONFIG_VGA_BIOS_FILE),)
endif # ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y)
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 0acb90ce7b..7a518167b3 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -482,15 +482,15 @@ unsigned long southcluster_write_acpi_tables(device_t device,
current = acpi_write_hpet(device, current, rsdp);
current = acpi_align_current(current);
-#if CONFIG_GOP_SUPPORT
- igd_opregion_t *opregion;
+ if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) {
+ igd_opregion_t *opregion;
- printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
- opregion = (igd_opregion_t *)current;
- init_igd_opregion(opregion);
- current += sizeof(igd_opregion_t);
- current = acpi_align_current(current);
-#endif
+ printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
+ opregion = (igd_opregion_t *)current;
+ init_igd_opregion(opregion);
+ current += sizeof(igd_opregion_t);
+ current = acpi_align_current(current);
+ }
ssdt2 = (acpi_header_t *)current;
memset(ssdt2, 0, sizeof(acpi_header_t));
@@ -544,7 +544,6 @@ __attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
{
}
-#if CONFIG_GOP_SUPPORT
/* Reading VBT table from flash */
static void get_fsp_vbt(igd_opregion_t *opregion)
{
@@ -615,4 +614,3 @@ int init_igd_opregion(igd_opregion_t *opregion)
return 0;
}
-#endif
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index ff3b1cd704..50d9577b16 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -20,10 +20,8 @@
#include <arch/acpi.h>
#include <soc/nvs.h>
-#if CONFIG_GOP_SUPPORT
#include <fsp/gma.h>
int init_igd_opregion(igd_opregion_t *igd_opregion);
-#endif
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void acpi_fill_in_fadt(acpi_fadt_t *fadt);
diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c
index d9bb98a8d1..315459b246 100644
--- a/src/soc/intel/common/vbt.c
+++ b/src/soc/intel/common/vbt.c
@@ -47,6 +47,9 @@ void *vbt_get(struct region_device *rdev)
{
void *vbt_data;
+ if (!IS_ENABLED(CONFIG_RUN_FSP_GOP))
+ return NULL;
+
/* Normal mode and S3 resume path PEIM GFX init is not needed.
* Passing NULL as VBT will not make PEIM GFX to execute. */
if (acpi_is_wakeup_s3())
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index c15e402052..12dd772249 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -77,6 +77,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select UDELAY_TSC
select ACPI_NHLT
+ select HAVE_FSP_GOP
config MAINBOARD_USES_FSP2_0
bool
@@ -87,7 +88,7 @@ config USE_FSP2_0_DRIVER
depends on MAINBOARD_USES_FSP2_0
default y if MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP2_0
- select ADD_VBT_DATA_FILE
+ select ADD_VBT_DATA_FILE if RUN_FSP_GOP
select SOC_INTEL_COMMON_GFX_OPREGION
select POSTCAR_CONSOLE
select POSTCAR_STAGE
@@ -97,7 +98,6 @@ config USE_FSP1_1_DRIVER
depends on !MAINBOARD_USES_FSP2_0
default y if !MAINBOARD_USES_FSP2_0
select PLATFORM_USES_FSP1_1
- select GOP_SUPPORT
select DISPLAY_FSP_ENTRY_POINTS
config CHROMEOS