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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-03-18 10:23:26 +0800 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-03-19 17:43:18 +0000 |
| commit | 34473ea6c9ee63de46b04b46cc47ef4aa5bae2b7 (patch) | |
| tree | b58d446167f4a033ae773287f2b7fd8f13b540a2 /src/soc | |
| parent | e82b02c004e94c4f6016543088f99120be415ff3 (diff) | |
| download | coreboot-34473ea6c9ee63de46b04b46cc47ef4aa5bae2b7.tar.xz | |
soc/intel/xeon_sp: Modify FSP-T code caching parameters
Use CACHE_ROM_BASE and CACHE_ROM_SIZE for code caching
parameters.
Tested on OCP Tioga Pass.
Change-Id: Ibba133d9f8fdfbdfae9a0e8e698356a3ca9ba424
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39625
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/bootblock/bootblock.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 6b2c48809d..dc88adc308 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -19,6 +19,7 @@ #include <intelblocks/fast_spi.h> #include <soc/iomap.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -29,8 +30,8 @@ const FSPT_UPD temp_ram_init_params = { .FsptCoreUpd = { .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, - .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), - .CodeRegionLength = (UINT32)CONFIG_ROM_SIZE, + .CodeRegionBase = (UINT32)CACHE_ROM_BASE, + .CodeRegionLength = (UINT32)CACHE_ROM_SIZE, .Reserved1 = {0}, }, .FsptConfig = { |