diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2017-01-21 16:55:03 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-01-22 19:24:37 +0100 |
| commit | 4234ca276419314a0df598c7375c683def67ab1a (patch) | |
| tree | 58b461f23eb243262e3a2e1e2588b31e6ae4e30d /src/soc | |
| parent | 367c9b328fd084509f8ed41ecf3c64ebc2e02e17 (diff) | |
| download | coreboot-4234ca276419314a0df598c7375c683def67ab1a.tar.xz | |
soc/intel/skylake: Include I2C code in romstage
The lpss_i2c driver is enabled in romstage, so the SOC needs to
export the pre-ram compatible I2C controller info, which for
skylake is in the bootblock/i2c.c file.
This was not causing a compiler error in normal use, but when
adding I2C debug code in romstage it failed to compile.
With this added, I can now do I2C transactions in romstage.
Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18198
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 3a474e725e..4b6fcfc1f1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -38,6 +38,7 @@ verstage-y += spi.c romstage-y += flash_controller.c romstage-y += gpio.c +romstage-y += bootblock/i2c.c romstage-y += memmap.c romstage-y += monotonic_timer.c romstage-y += me.c |