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| author | Deepa Dinamani <deepad@codeaurora.org> | 2014-05-13 13:49:42 -0700 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-03 05:00:08 +0100 |
| commit | 4d2d6ca79a03f60f28c8f8bc7591483260a15c1b (patch) | |
| tree | 42adc2b1deb0bcb3a986c3e1e2157e793bff5ade /src/soc | |
| parent | 41a5d0df58754b75cfe5c79271ae383f3d5976c1 (diff) | |
| download | coreboot-4d2d6ca79a03f60f28c8f8bc7591483260a15c1b.tar.xz | |
soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
Define a base address for page table entries. Place it 64KB below the
bootblock loading address.
BUG=chrome-os-partner:28467
TEST=verified that the page tables are being populated at this
address. Also observed that the SPI driver takes 900 ns to
process a byte as opposed to 1.5 us in case caching is not
enabled.
Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200332
(cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068
Reviewed-on: http://review.coreboot.org/8009
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 4f081f047e..3752c166a6 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -70,4 +70,8 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00016000 +config TTB_BUFFER + hex "memory address for page tables" + default 0x405f0000 + endif |