diff options
| author | Lin Huang <hl@rock-chips.com> | 2017-08-03 14:51:41 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-08-06 23:21:02 +0000 |
| commit | 7c5eb073e784a334d295bc533c07df827e47839e (patch) | |
| tree | d5fc9c29745edcd16d3eb144251f5aa8d65f339f /src/soc | |
| parent | 589474fec768f7dcc95222c5791839f16c1d7e6e (diff) | |
| download | coreboot-7c5eb073e784a334d295bc533c07df827e47839e.tar.xz | |
rockchip: gpio: Correct rk3399 pmu gpio pull setting
Starting with RK3399, PMUGPIO pull registers use the same write mask
format as normal GRF registers, so they need to use RK_CLRSETBITS()
rather than clrsetbits_le32().
BRANCH=None
BUG=None
TEST=boot from scarlet
Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/rockchip/common/gpio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 952500974e..1d87cf814d 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -31,7 +31,7 @@ static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); - if (is_pmu_gpio(gpio)) + if (is_pmu_gpio(gpio) && IS_ENABLED(CONFIG_SOC_ROCKCHIP_RK3288)) clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), pull_val << (gpio.idx * 2)); else |