diff options
| author | Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> | 2018-03-07 09:00:05 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-03-09 17:12:15 +0000 |
| commit | 8da81da3b9400763f066762dbf9a203f3892fabd (patch) | |
| tree | d145a6332187eb0901e3d59b0e8f5386eb82a3e8 /src/soc | |
| parent | 9858bd2e3d511ce943207b1e82a9f75853fa637d (diff) | |
| download | coreboot-8da81da3b9400763f066762dbf9a203f3892fabd.tar.xz | |
soc/amd/stoneyridge: Add function to enable I2C host controllers
In preparation for moving AGESA calls out of bootblock:
Add function to enable the four stoneyridge I2C engines.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)
Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 20 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 88403e61ad..cccdf9736f 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -344,6 +344,7 @@ struct soc_amd_stoneyridge_gpio { void sb_enable_rom(void); void configure_stoneyridge_uart(void); +void configure_stoneyridge_i2c(void); void sb_clk_output_48Mhz(void); void sb_disable_4dw_burst(void); void sb_enable(device_t dev); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index c591c69d64..367c565486 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -320,6 +320,26 @@ void configure_stoneyridge_uart(void) } while (!status); } +void configure_stoneyridge_i2c(void) +{ + bool status; + + /* Power on the I2C devices */ + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C0); + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C1); + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C2); + power_on_aoac_device(FCH_AOAC_D3_CONTROL_I2C3); + + /* Wait for the I2C devices to indicate power and clock OK */ + do { + udelay(100); + status = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); + status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); + status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); + status &= is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + } while (!status); +} + void sb_pci_port80(void) { u8 byte; |