diff options
author | Shamile Khan <shamile.khan@intel.com> | 2016-09-01 13:36:50 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2016-09-06 20:22:27 +0200 |
commit | 93c54704340e27ba219baaced952bc3d8bc52695 (patch) | |
tree | a3b2c51aaf23e5c72bd908a5a056f9602ce4730c /src/soc | |
parent | 37ddb630dd4d7c7a567302d84a814756bf36d7b4 (diff) | |
download | coreboot-93c54704340e27ba219baaced952bc3d8bc52695.tar.xz |
google/reef: Enable 20K pull ups for LPC CLKRUN and LAD0:3 lines
The pull up for CLKRUN is required to resolve keyboard slowness
and malfunctioning observed on some reef systems. The CLKRUN
signal was probed and found to be floating when the pull up
was not enabled. Also Added pull ups for the LPC Multiplexed
command, address and data lines LAD0:3 because the LPC
Interface specification requires them.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=When a key is pressed, the character is immediately visible
on the screen. Also the interrupt count for i8042 increments
immediately in /proc/interrupts.
Change-Id: I16df1a0301a3994c926a609f61291761219f9e01
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/16426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
-rw-r--r-- | src/soc/intel/apollolake/lpc_lib.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c index 7627fea58d..f435047f28 100644 --- a/src/soc/intel/apollolake/lpc_lib.c +++ b/src/soc/intel/apollolake/lpc_lib.c @@ -47,10 +47,11 @@ static const struct lpc_mmio_range { static const struct pad_config lpc_gpios[] = { PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) |