diff options
| author | Lin Huang <hl@rock-chips.com> | 2017-02-22 18:22:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-06-19 18:43:19 +0200 |
| commit | aaf6322a1172d4833c6f190616db6f27dcd77377 (patch) | |
| tree | 080342fd44b8348313c61c956fb0ec00e4ef7e78 /src/soc | |
| parent | 9a848dde8b34a854af716670f5c993c49c1ab22e (diff) | |
| download | coreboot-aaf6322a1172d4833c6f190616db6f27dcd77377.tar.xz | |
rockchip/rk3399: fix DRAM gate training issue
The differential signal of DQS needs to keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it. But if it has PHY side ODT
connected at this time, it will change the DQS
signal level. So it needs to disable PHY side ODT
when doing gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f
Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448278
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/rockchip/rk3399/sdram.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index e51cd8968d..97346796fe 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -633,6 +633,7 @@ static int data_training(u32 channel, u32 i, tmp; u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; u32 rank = sdram_params->ch[channel].rank; + u32 reg_value = 0; /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ setbits_le32(&denali_phy[927], (1 << 22)); @@ -741,6 +742,28 @@ static int data_training(u32 channel, /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { + + /* + * The differential signal of DQS needs to keep low level + * before gate training. RPULL will connect 4Kn from PADP + * to VSS and a 4Kn from PADN to VDDQ to ensure it. + * But if it has PHY side ODT connect at this time, + * it will change the DQS signal level. So disable PHY + * side ODT before gate training and restore ODT state + * after gate training. + */ + if (sdram_params->dramtype != LPDDR4) { + reg_value = (read32(&denali_phy[6]) >> 24) & 0x7; + + /* + * phy_dqs_tsel_enable_X 3bits + * DENALI_PHY_6/134/262/390 offset_24 + */ + clrbits_le32(&denali_phy[6], 0x7 << 24); + clrbits_le32(&denali_phy[134], 0x7 << 24); + clrbits_le32(&denali_phy[262], 0x7 << 24); + clrbits_le32(&denali_phy[390], 0x7 << 24); + } for (i = 0; i < rank; i++) { select_per_cs_training_index(channel, i); /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ @@ -784,6 +807,18 @@ static int data_training(u32 channel, write32((&denali_pi[175]), 0x00003f7c); } clrbits_le32(&denali_pi[80], 0x3 << 24); + + if (sdram_params->dramtype != LPDDR4) { + /* + * phy_dqs_tsel_enable_X 3bits + * DENALI_PHY_6/134/262/390 offset_24 + */ + tmp = reg_value << 24; + clrsetbits_le32(&denali_phy[6], 0x7 << 24, tmp); + clrsetbits_le32(&denali_phy[134], 0x7 << 24, tmp); + clrsetbits_le32(&denali_phy[262], 0x7 << 24, tmp); + clrsetbits_le32(&denali_phy[390], 0x7 << 24, tmp); + } } /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ |