diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2014-09-29 08:38:04 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:55 +0200 |
| commit | cdcc9a4635ab8f5f40a143d5d297418206a412ee (patch) | |
| tree | 1744d2dddaec2d0388967c507c8041ef4fb2da09 /src/soc | |
| parent | 635ee51b0d5cffc155e09fbbe644c2914ce54b6a (diff) | |
| download | coreboot-cdcc9a4635ab8f5f40a143d5d297418206a412ee.tar.xz | |
broadwell: Add event log entry for GPIO27
Add event log entry if GPIO27 is used to wake the system.
This GPIO is treated separately from other GPE and it is
one of the only events that can wake from Deep Sx.
BUG=chrome-os-partner:31549
BRANCH=samus
TEST=samus: suspend/resume and wake from keypress, check for
GPIO27 event in event log.
Change-Id: If699640701b0afcd0843c2a99546ee6bb9d09361
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 0f1cccfd00552dafbaa91acc362b5e35474c3a95
Original-Change-Id: I38a44a62f68288a4ae3f97fe078ca222fd01390a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220323
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9213
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/elog.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index bb7e7ba4d2..30f64e00fe 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -63,6 +63,10 @@ static void pch_log_wake_source(struct chipset_power_state *ps) if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); + /* GPIO27 */ + if (ps->gpe0_sts[GPE_STD] & GP27_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27); + /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32); |