diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-01 16:50:27 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-25 22:31:28 +0100 |
| commit | d25ead2589c47ae476975cb6c42354c3a12fb3f9 (patch) | |
| tree | 99f08fb783800efae7cc9af6403479e9d2994df7 /src/soc | |
| parent | e06771c74ebf3b307b6b8690c9c68233bbee14ac (diff) | |
| download | coreboot-d25ead2589c47ae476975cb6c42354c3a12fb3f9.tar.xz | |
tegra132: introduce romstage_mainboard_init()
Instead of calling out with function names all the possible
combinations of interface and device provide one call to the
mainboard to configure all the necessary bits.
BUG=chrome-os-partner:31104
BUG=chrome-os-partner:31105
BRANCH=None
TEST=Built and ran on rush.
Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d
Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210838
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8901
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/romstage.h | 6 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/romstage.c | 32 |
2 files changed, 29 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra132/include/soc/romstage.h b/src/soc/nvidia/tegra132/include/soc/romstage.h index dcf6ad6079..14358d8d58 100644 --- a/src/soc/nvidia/tegra132/include/soc/romstage.h +++ b/src/soc/nvidia/tegra132/include/soc/romstage.h @@ -20,10 +20,10 @@ #ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ #define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ +void romstage(void); +void romstage_mainboard_init(void); + void mainboard_configure_pmc(void); void mainboard_enable_vdd_cpu(void); -void mainboard_init_tpm_i2c(void); -void mainboard_init_ec_spi(void); -void mainboard_init_ec_i2c(void); #endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index be431f7975..8d12dedaf1 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -32,7 +32,25 @@ #include <soc/clock.h> #include <soc/romstage.h> -void romstage(void); +void __attribute__((weak)) romstage_mainboard_init(void) +{ + /* Default empty implementation. */ +} + +static void *load_ramstage(void) +{ + void *entry; + /* + * This platform does not need to cache a loaded ramstage nor do we + * go down this path on resume. Therefore, no romstage_handoff is + * required. + */ + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/ramstage"); + + return entry; +} + void romstage(void) { void *entry; @@ -67,12 +85,14 @@ void romstage(void) ccplex_load_mts(); printk(BIOS_INFO, "T132 romstage: MTS loading done\n"); - mainboard_init_tpm_i2c(); - mainboard_init_ec_spi(); - mainboard_init_ec_i2c(); + romstage_mainboard_init(); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/ramstage"); + entry = load_ramstage(); + + if (entry == NULL) { + printk(BIOS_INFO, "T132 romstage: error loading ramstage\n"); + clock_halt_avp(); + } cbmemc_reinit(); |