diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-03-05 11:54:47 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-30 09:42:55 +0000 |
| commit | e5565c45cb71df105bc9ff1dc7572b4e749adaea (patch) | |
| tree | e000066c58d5c33bd6ec73fef90bc83f25a78213 /src/soc | |
| parent | 991ee05de9fedc15f178660e0cac0b46e783525e (diff) | |
| download | coreboot-e5565c45cb71df105bc9ff1dc7572b4e749adaea.tar.xz | |
soc/intel/{icelake, tigerlake}: Remove DDI A lane programming
For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by
default. And kernel driver no longer relies on coreboot to provide
information via DDI_BUF_CTL_A(for DDI port A) register programming.
Hence removing this code.
BUG=b:150788968
BRANCH=None
TEST=checked jslrvp and tglrvp compilation and boot.
Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/icelake/graphics.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/graphics.c | 19 |
2 files changed, 0 insertions, 38 deletions
diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 4f5d573c8b..0ee340ce3b 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -31,24 +30,6 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { - uint32_t ddi_buf_ctl; - - /* Skip IGD GT programming */ - if (CONFIG(SKIP_GRAPHICS_ENABLING)) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig diff --git a/src/soc/intel/tigerlake/graphics.c b/src/soc/intel/tigerlake/graphics.c index fef17e17e8..4054bd549b 100644 --- a/src/soc/intel/tigerlake/graphics.c +++ b/src/soc/intel/tigerlake/graphics.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/opregion.h> #include <intelblocks/graphics.h> #include <types.h> @@ -37,24 +36,6 @@ uintptr_t fsp_soc_get_igd_bar(void) void graphics_soc_init(struct device *dev) { - uint32_t ddi_buf_ctl; - - /* Skip IGD GT programming */ - if (CONFIG(SKIP_GRAPHICS_ENABLING)) - return; - - /* - * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. - * This will allow the kernel to use 4-lane eDP links properly - * if the VBIOS or GOP driver do not execute. - */ - ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - if (!acpi_is_wakeup_s3() && !(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) { - ddi_buf_ctl |= (DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED | - DDI_BUF_IS_IDLE); - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); - } - /* * GFX PEIM module inside FSP binary is taking care of graphics * initialization based on RUN_FSP_GOP Kconfig |