diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-11 08:39:54 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-02-16 20:37:22 +0100 |
| commit | f3f409bf5592dc093dc7f2dc1448ad21879c466e (patch) | |
| tree | 289aa17ccfff976c618ff02998b5a89c123397f3 /src/soc | |
| parent | 9d9d7f04296e2c6de5bd10ee4bff1a496006f9e1 (diff) | |
| download | coreboot-f3f409bf5592dc093dc7f2dc1448ad21879c466e.tar.xz | |
baytrail: correct MMC pci location
The original documentation was incorrect. Fix the pci
device for the MMC port to reflect reality.
MMC is at 00:17.0 with a device id of 0x0f50.
BUG=None
BRANCH=None
TEST=Built.
Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172772
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4884
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/pci_devs.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 46c6ea6f41..8b0335e3ea 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -32,11 +32,6 @@ #define GFX_FUNC 0 # define GFX_DEVID 0x0f31 -/* MMC Port */ -#define MMC_DEV 16 -#define MMC_FUNC 0 -# define MMC_DEVID 0x0f14 - /* SDIO Port */ #define SDIO_DEV 17 #define SDIO_FUNC 0 @@ -63,6 +58,11 @@ #define LPE_FUNC 0 # define LPE_DEVID 0x0f28 +/* MMC Port */ +#define MMC_DEV 23 +#define MMC_FUNC 0 +# define MMC_DEVID 0x0f50 + /* Serial IO 1 */ #define SIO1_DEV 24 # define SIO_DMA1_DEV SIO1_DEV |