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| author | Aaron Durbin <adurbin@chromium.org> | 2018-04-12 14:00:45 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-04-16 02:25:28 +0000 |
| commit | fa529bb940a413d95322e22b29c29531f4721d52 (patch) | |
| tree | 79351c581c8cbcbebea70f4f3c217544d441e172 /src/soc | |
| parent | cee8532ce38a03528a6c9b7a4875d33840ba362e (diff) | |
| download | coreboot-fa529bb940a413d95322e22b29c29531f4721d52.tar.xz | |
soc/intel/apollolake: update cache options for glk
On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.
BUG=b:72728953
Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 029695d08a..2a2782e894 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -143,6 +143,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex + default 0x100000 if SOC_INTEL_GLK default 0xc0000 help The size of the cache-as-ram region required during bootblock @@ -334,6 +335,7 @@ config CACHE_QOS_SIZE_PER_BIT config L2_CACHE_SIZE hex + default 0x400000 if SOC_INTEL_GLK default 0x100000 config SPI_FLASH_INCLUDE_ALL_DRIVERS |