diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-11-23 18:03:46 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-04 16:39:33 +0000 |
| commit | 8cee45c3f8f05d936ba181f56405b8c936666a36 (patch) | |
| tree | 36e0cf79a1438e53b28ff51d0c6b5c9d7bd83cb8 /src/southbridge/amd/agesa/hudson/Makefile.inc | |
| parent | 55009af42c39f413c49503670ce9bc2858974962 (diff) | |
| download | coreboot-8cee45c3f8f05d936ba181f56405b8c936666a36.tar.xz | |
sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initialization
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/amd/agesa/hudson/Makefile.inc')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/Makefile.inc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5cb3755e8b..5c921280f7 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,7 +17,12 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -bootblock-y += enable_usbdebug.c +ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +bootblock-y += bootblock.c +bootblock-y += early_setup.c +bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c +endif + romstage-y += enable_usbdebug.c ramstage-y += enable_usbdebug.c romstage-y += early_setup.c |